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| DECEMBER, 19= .- ,. : This document contains information on a new product. Specifications and information herein are subject 10 change without notice. @MOTOROLA INC., 1%3 AD1-~ .. . Motorola reserves the right to make changes to any products herein to improve reliability, function or design. Motorole does not assume any Iiabilityarising out of the application or use of any product or circuit dewri~ herein; neither does it convey any license under its patent rights nor the rights of othars. `. r Requesting Bus Master Service . . . . . . 1. . . . . . . . ... . . . . . . . . . . . . . . . . . . . . . . Vectored, Prioritized Portlnterrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Autovectored Port interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Request Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Direct Method of Resetting Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Handshake Pin Sense Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enabling Ports Aand B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PortAand BAlternate Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2-5 2-5 2-6 2-6 2-7 2-7 2-7 .-. TABLE OF CONTENTS (Continued) Paragraph Number Page Number `$: ?$$~:t<>$+* ..,.33$ ,.:,{\ . \J~ ,.$... .$W* Section 3 .J., ~ .' J:.$,, ~<,t<,:,i,.i ,~\,,,, >`t~,~., Port Modes }:<,...~.>.~.. ,`" ` . .<::#-l Port A Control Register . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..$f~...h Port BControl Regis?er. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..i.p..~~~~' 3-1 Mode O- Unidirectional 8-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . ..k. J*i?+a@}?.3-2 ~.\* ~~)~> ,"$::$, Submode 00 - Pin-Definable DoubleBuffered input or .J4.~:,$y: ,~!.!,: .{$r.i,,,~$,, SingleBuffered Output . .. ~' . . . . . . . . . . . . . . . . . . . . ..f~~~~$$ . . . . . . . .,!'. 3-2 Title 3.1 3.2 3.3 3.3.1 3.3.2 . Submode Ol - Pin-Definable ~oubleBuffered Output,~~~,& Non-Latched Input . . . . . . . . . . . . . . . . . . . . . . . . . ..'i~$~~~. . . . . . . . . . 3-4 3.3,3 SubmodelX- Bit 1/0 (Pin-Definable SingieBy%@re& Output or ~ :t\\~:.\\.'., ~~<.~y Non-Latched Input) . . . . . . . . . . . . . . . . . . . ~i$:;*'.*~.,\. . . . . . . . . . . . . . . .\$*Tk. . 3-6 16-Bit Mode... . . . . ..i. !$t.c~~ . . . . . . . . . . . . . . . . . . 3.4 Mode 1 -Unidirectional 3-8 3.4.1 Port A Control Register.....:.. . . . . . . ..~~! . . . . . . . . . . . . . . . . . . . . . . 3-9 ~$,)!i:"~):* . . . . . . . . . . . . . . . . . . . . . 3.4.2 Port B Control Register. . . . . . . . . . . ..i.$ ~...,.... . . 3-9 3.4.3 Submode XO - Pin-Definable Doq-~&ffered Input or SingleBuffered Output . . . . ..~$$&.w.J~.. . . . . . . . . . . . . . . . . . . . . . . . . .. 3-9 ,, 3.4.4 Submode Xl - Pin-Definable'W&%leBuf feredOutputor Non-Latched input . . . . . . ..$F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...3-12 .. " 3.5 Mode2-Bidirectiona18-Bit~~de.... ............................... 3-14 3.5.1 ": Port A Bit 1/0 (Pin-Q~f~~a~!e SingleBuffered Output or ,, Non-Latched lnW~~~-? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ,. 3-14 3.5.2 Port BDoubl*Rq~$$@l /O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 . 3.5.2,1 `Doubl+,~h~@@d input Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 3.5.2.2 Doubl.&B~fi&redO utputTransfers.. ., . . . . . . . . . . . . . . . . . . . . . . . . 3-15 3,6 Mode3- B~~tej$%$~nal 16-Bit Mode... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3.6.1 DouQ&~u$fered input Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 D,@$$,@+~uffered Output Transfers.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 3.6.2 ~,, yp ~b~.:> ,,. ..,,... ,",,,t,,,. .,., Section 4 i,. ~:$'" ,,? ,*+, ,:1..,~;},~t},. .,,:> Programmer's Model 4.1 ,$~~#&rt General Control Register (PGCR).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2$..+PPortSewice ~ RequestRegist er(PSRR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 ~:~ $$> Port Data Direction Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 ,;Y ( "-' ` . iv + TABLE OF CONTENTS (Concluded) Paragraph Number 4.7 4.7.1 4.7.2 4.8 4.9 4..10 4.11 4.12 4.13 4.14 -,- Title Page Number+::~$:$, ,,.,..~$, ,* ! <":.., ~~i:,$p Port Alternate Registers . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port AAlternate Register (PAIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , $$8'?' ,+ Port BAlternate Register (PBAR) . . . . . . . . . . . . . . ....' . . . . . . . . . . . . . . ..gF `+~*"4-6 Port State Register (PSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..F#?'lY.. `:*$, Timer Control Register (TCR) . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . ..w.. *~$ 4-6 4-8 TimerInterrupt Vector Register (TIVR) . . . . . . . . . . . . . . . . . . . . . . ..'~~~~,,..:". Counter Preload Register H, M, L (CpRH-L) . . . . . . . . . . . . . . . . .~-~~$~~.. . . . 4-8 ....... 4-8 Count Register H, M, L(CNTRH-L) . . . . . . . . . . . . . . . . . . . . ..}~$${f .. 48 Timer Status Register (TSR) . . . . . . . . . . . . . . . . . . . . . . . ... .~$~?~ . . . . . . . . . `4-9 RegisterValueAfter Reset . . . . . . . . . . . . . . . . . . . . . . ..q~.#j& . ... . . . . . . . . . . ,..$.<'$$~ ~:.*,.,,,~ ~($+,?< ,,, `+:5A3F ,..$? Section 5 Timer Operation and AppliHtj~S{$~mmaw Timer Operation . . . . . . . . . . . . . . . . . . . . . . ...".'.~~*.i. . . . . . . . . . . . . . . . . . . . . . .. Run/HaltDefinition . . . . . . . . . . ..t.&~} .. ........................ Timer Rules . . . . . . . . . . . . . . . ..*~.~.~V+'.. . . . . . . . .. . . . . . . . . . . . . . . . . . . Timer lnterruptAcknowledgeCy??$J? ............................. Timer Applications Summary.,)+. .>$ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Periodic interrupt Gener@(~?&le. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -Square Wave Gener:J~$$z, .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lnterruptAfterTim~:W;3 ....... ................................. Elapsed Time ~:e,~~@entExamples ............................. System QQ~Sxample . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exter+R#~&l#ck . . . . . . . . . . . . . . . . . . . ; . . . . . . . . . . . . . . . . . . . . . . . . . Device,~~t~dog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .,\ ..~,!>+i,. ,*!, `.~p$k,. .*y**.,\,,hkx8,. ,.JV,. \>,.!, Section6 ..".<. `* . :<.,, ,Q,.v Electrical Specifications 5-1 5-1 5-2 5-2 5-2 5-3 5-3 5-4 5-5 5-5 5-6 5-6 .`) .' ~, 5.1.1 5.1.2 5:1.3 5.2 5.2.1 5i2.2 5.2.3 5.2.4 5.2.4.1 5.2.4.2 5.2.5 6.1 ~~$~~~rn Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 ,~:*.@~ttialCharactetistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 ,.)}~%owerConsiderations . . . . . . . . . . . . . ... . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 614'~$~''* DCElectricalCharacteristics . . . . . . . . .{ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .~?k.~" AC Electrical Specifications - Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . ,$,:;?''" AC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . `.~$,i. `I*:?..,:{,. `>,$' 1: Section 7 Mechanical Data and Ordering information Pin Assignment . . . . . . . . . . . . . . . . . . . . . . ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 7.2 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6-1 6-1 6-2 6-3 6-4 7-1 7-2 7-2 Hgure Numbr 1-1 1-2 1-3 2-1 1-2 14 1-6 2-3 24 2-6 2-6 5-3 54 5-5 ,.-_, ( &6 LIST OF TABLES Table Number 1-1 Wtle Port Mode Control Summav . . . . . . . . . . . . . . . . . . . . . . . 1-3 1-6 1-8 2-5 3-2 3-8 3-14 3-16 3-18 4-1 4-3 4-5 5-2 .................... .................... .................... .................... a ` SECTION 1 INTRODUCTION ~;:,k::$\.. . .>,,,,,:*" ..,-\,i,,,., .l~,.~ .-!".V " ` `!.$> .,,:,'<*,, ~ .,,,,:.$.> "?is$~. ,,3: ., ,.,,$ $,* ,.\,\~\}y, ..-,,.$R:~ .,...,!:i' ",$. ,,,,.:".>?'?s > y.:t.. FJ,j. .,:s. ,}1;*+ ~ *J,:\~j,~- :,`{., .. .~,,, ~ ~*~.*. ,>..,,. ,,.~: \\., .s~?-s The MC68230 parallel interface/timer (P1/Tl provides versatile double buffered,$ar~i~~ interfaces and a system oriented timer for M68000 systems. The parallel interfaces oper~~~$~$nidirectional or bidirectional modes, either 8 or 16 bits wide. In the unidirectional modes, afl,?$$sciated data direction register determines whether each port pin is an input or output. In ?$f.jp.$?)<>. .ti&@#rectional modes the data direction registers are ignored and the direction is determined d,y,na~~c~lly by the state of four handshake pins. These programmable handshake pins provide an inf&f@ce flexible enough for connection to a wide variety of low, medium, or high speed peripheq~~~$$ather computer systems. The Pi/T ports allow use of vectored or autovectored interrupts, ~~g$~is~ provide a DMA request pin for connection to the MC68450 direct memory access contr@ler'!Q,MAC) or a similar circuit. The Pi/T timer contains a 24 bit wide counter and a 5-bit prescal@.~he timer may be clocked by the system clock (Pi/T CLK pin) or by an external clock (TIN fiy~$nd a 5-bit prescaler can be u'sed. It can generate periodic interrupts, a square wave, or a $$~~~~terrupt after a programmed time pefiod. It can also be used for elapsed time measurement 0*.ss a device watchdog. ,, ,,. ,$::* . \.J):' `+'t.,,, `, Features of the Pi/T include: .:,, \ ,+,/ ~@+QJ~* consists of two logically independent sections: the ports and the timer. The port section ~+,~~~~f~tsof POfl A (pAO-PA7), port B (PBO-PB7), four handshake pins (HI, H2, H3, and H4), two $~~neral input/output (1/0) pins, and six dual-function pins. The dual-function pins can individually ~'operate as a third port (port C) or an alternate function related to either port A, port B, or the timer. The four programmable handshake pins, depending on the mode, can control data transfer to and from the ports, or can be used as interrupt generating inputs or 1/0 pins. Refer to Figure 1-1. The timer consists of a 24-bit counter, optionally clocked by a 5-bit prescaler. Three pins provide complete timer 1/0: PC2/TIN, PC3/TOUT, and PC7/TIACK. Only the ones needed for the given configuration perform the timer function, while the others remain port C 1/0. -' ) ,, 363940 Vss ,, 4++ RESET CLK 41 42 ` C% DTACK 4 43 R/~ 44 DO 45 D1 46 D2 47 D3 4S 04 1 05 2 D6 3 D7 r # `j ,, ,, Port Interrupt/ DMA Control Logic ., 8 9 10 11 12 Controllers and 13 14 15 16 ,., ~, -... Timer ., .,,. ~PBO ~PBl ~PB2 ~PB3 ~PB4 ~PB5 ~PB6 ~PB7 17 18 19 20 21 22 23 24 ,, PC71 37 % ~Ji\? ,*$ ,.:. t$,,y,,.:\> ~ .:$, *i\, .,?~ Pc4/ pc3/TouT Pc2/TIN Pcl Pco tt?tt RS1 ~ RS2 28 RS3 27 RS4 26 RS5 25 Figure 1-1. Block Diagram ~ *$ ,, ... ,t::,.j.j.i :$. *:,:+\ ~,, .',.? A!.t~~.'. `.yif\3, !+}':?,,. A&, ,$~+~. Thq,w$t~.m bus interface provides for asynchronous transfer of data from the Pi/T to a bus master ~M#*t$& data bus (DO-D7). Data transfer acknowledge (DTACK), register selects (RS1-RS5), timer `~~wpt acknowledge (TIACK), read/write line (R/~), chip select (~), or port interrupt `$~;~knowledge (PIACK) control data transfer between the Pi/T and an Mm. ,.,. `!.:, 1.1 PORT MODE DESCRIPTION The primary focus of most applications will be on port A, port B, the handshake pins, the port interrupt pins, and the DMA request pin. They are controlled in the following way: the port general control register contains a 2-bit field that specifies one of four operation modes. These govern the \ .... \ 1-2 >. ,* overall operation of the ports and determine their interrelationships. Some modes require additional information from each port's control register to further define its operation. In each port control register, there is a 2-bit submode field that serves this purpose. Each port mode/submode combination specifies a set of programmable characteristics that fully define the behavior of that port and "\\:s, *)*< .k\& two of the handshake pins. This structure is summarized in Table 1-1 and Figure 1-2. ~N,? .,\..y$<$ .,,. ,.<,.,, y "::$~ ,Jk>, ~ $t>4* y?: <,~:]. ` 1~ .. ,i,$ra,i.,c~' ,.*,.,, Table 1-1. Poti Mode Control Summa~ ?{]*;?.{: ,:,<.,,*i:,, 1, ..k,k\\\: Mode O (Unidirectional &Bit Mode) j.: ~:i,`+'" Port A `::: >..:** ~:~, ,Sy Submode ~ - Pin-Definable Doubl&Buffered Input or SingI%Buffered Output .t$, l)ii~.!,,, `.,~ .,t$}:;.~, H1 - Latches input data ~ ~?:.. ."ti$ ,:1, . or H2 - Status/interrupt generating input, general-purpose output, or operation wtf~ ~+~$ the interlocked ,: ?. ~,.#? , !**\*. :, pulsed handshake protocols $."~:i>.+*' Submode 01 - Pin-Definable Doubt&Buffered Output or Non-Latched Input ~~?:$%" .:,: H1 - Indicates data received by peripheral H2 - Status/interrupt generating input, general-purpose output, or .~~~on''hth H 1 in the interlocked or .,;!:.* {%*.,.\ \` pulsed handshake protocols ~ .,&<\, $.>.. .!*". Submode 1X - Pin-Definable SingleBuffered Output or Non-Latc~~. Intit .,'.?,`*J$ ..:.' > .... H1 - Status/interrupt generating input ?ftqF\ ""` H2 - Status/interrupt generating input or general-purpq o~~pt ,fe;;:i.$ Port B `J `+,:+,. ,,F>..v*\i,@ \ .)1$ H3 and H4 - Identical to port A, H1 and H2 ii}, ?$j . t:<\\,\~.'$3 \t.,#$* Mode 1 (Unidirectional l&Bit Mode) .$.'.:;\{(h ....+<.., . Port A - Most-Significant Data Byte or Non-Latched lwt~r Singl~Buffered Output Submode XX - (not used) *$fj ,, H1 - Status/interrupt generating in@~~ ~ ; H2 - Status/interrupt generating ~p~k~r general-purpose output Port B - Least-Significant Data BVte , +~~,J~$, Submode XO - Pin-Definable D@~&~ffered Input or Single Buffered Output H3 - Latches input data~&~~$<<:JiF H4 - Status/ intermp~ emjhg input, general-purpose output, or operation with H3 in the interlocked or Pul,ed handsmkg~~tocols Submode Xl - Pin-D&~n;&@ ~oubl&Buffered Output or Non-Latched Input H3 - lndicate~~&t~Weived bv peripheral H4 - Sta$~,q+~~,@pt generating input, general-purpose output, or operation with H3 in the interlocked or pul~$ h%dshake protocols .,>,, v%.,,;:$ . ~:"~: Mode 2 (Bidirectioh~,~it Mode) Port A ~~~$ I/@' S@~~~@XX - (not used) `;: * Poyi$i:.$ik ~ubl&Bu~fered Bidirectional Data ~$~$,$ti~ode XX - (not used) ;S:ia+,+ H1 - indicates output data received bv the peripheral and controls output drivers .Y+ti ~ ,,. .*, ,. "*$'>.., \+;.*.J~ >,$< ~ ~' H2 - Operation with H1 in the interlocked or pulsed output handshake protocols ,; , `.% ~~ ~!~ :,,? :,* H3 - Latches input data ,, +,F 8 H4 - Operation with H3 in the interlocked or pulsed input handshake protocols \-!$~.i:.'.Mode 3 (Bidirectional 16 Bit Mode) Port A - Doubl&Buffered Bidirectional Data (Most-Signifi@nt Data Byte) Submode XX - {not used) Port B - Double Buffered Bidirectional Data (Least-Significant Data BVte) Submode XX - (not used) H 1 - Indicates output data received bv peripheral and controls output drivers H2 - Operation with H1 in the interlocked or pulsed output handshake protocols H3 - Latches input data H4 - Operation with H3 in the interlocked or pulsed input handshake protocols ,.?, .3.8 .,..+.. ~\+\.l.i, .{ >,,,*, . ,..:,$,,~:>~ +$., ,.$`k ,,$: --.. LEGEND: a[ = DoubleB.ffered `)sing'eBuffed MODE O SUBMOOE ~ RmDdnable Doubl&Buffered Input or Sngl*Buffered Output ..,. [, MODE O .< SUBMODE 01 PimDdnable Doubl+Bufferad Q ~,, or NomLatchd Input ~ `k.$ "~ I I MODE 1 PORT B SUBMODE XO PimDtirrablti DoubleBuffered Input or Singl&Bufferad Output Figure 1-2. POR Mode Layout (Sheet 1 of 2) M C6B230 MODE 1 PORT B SUBMODE Xl Pi* Definable Doubl&Buffered Output or Nom Latchd Input I E +--- H2 H3 H4 1 . .: x! ` "%:: `!~.~: *a ,:.>, ..i f,;:): ~ ,ti".,~,]:-.>.. ..,!* ~ ,$ ,<:,, A and B (16) H1 HZ *) < H3 H4 *}" Input Transfers `, Output Transfers , MODE 3 Bidirectional l&Bit ,. ,+ >,, ~,i::t~$.. MC6S230 h:) .:, -\,,.\. ,..>:$>, ,.~l$: ,* :>X$,.?-O .i.:i,,, .. ,. . ..)..;: `+> ~" ,.,,.,>$$' "1$,,,, ,:. :,'$,,,,$. : }i,.$y .,*,,%, s.? ~,$.,.~..,i. .,.:<$,. ,,,*, . ., .,.!~.....* ..L \ .*]J.\ . < ?.<, ~+ .,l `~?, . .:>$' .,,;,.;$$l?>.: -,,+~,+1 1.2 SIGNAL DE~,@jR~ON ,p~~$e 1-2.Pon Mode Layout (Sheet 2 of 2) ~ ~,~$ .-:::, Throughout ~~is dw' sheet, signals are presented using the terms active and inactive or asserted and negat~$~~{~~pendent or whether the signal is active in the high-voltage state or low-voltage state. (~$a~~gt)vestate of each logic pin is giyen below. ) Active low signals are denoted by a supers"$~~%,. bar. R/~ indicates a write is active low and a read active high. Table 1-2 further dq,~~iseach pin and the logical pin assignments are given in Figure 1-3. ::> ~::. >>.., ~ *: .,.i*3* ~ ,l*. <$ .P;* ~~$$~zl Bidirectional Data Bus (DO-D7) ?l\,*$ k, The data bus pins, DO-D7, form an 8-bit bidirectional These pins are active high. 1.2.2 Register Selects (RS1-RS5) The register select pins, RS1-RS5, are active high high-impedance inputs that determine which of the 23 internal registers is being selected. They are provided by the M88000 bus master or other bus master. .. data bus to/from an MW~ bus master. --- 1-5 Table 1-2. Signal Summary Signal Name " CLK m Input/Output Input Input Input/Output output output Input Input or Output Adve State Edge/ Level Senstive Falling and Rising Edge Lavel Level output states Low High= 1, Low=O Low Low Low or High Low or High High=l, Low=O ~D7 DMAREQ m H1(H3}*** H2(H4)* * PA& PA7**, PBGPB7'*, High, Low, High Impe High, Low High, Low, High lmEQ@ Asserted Edge Asserted Edge Level High, Low, Hi@' [rn@nce High, Loy&~~Mj,@dance Input/Output, PCO-PC7 PIACK ` m RS1-RS5 R/w m m TIN (External Clock) TIN (Run/Halt) TOUT (Square Wave) TOUT (~) q qq Input or Output Input output Input Input input Input Input Input output output Low Low High= 1, Low=O High Read, Low Write Low Low High Low Low Level , .;i, ;?y( ..:.:. .,! `>?:,.,.:?$ q* ' Pullupresistors required. Note these pins have internal pUllUp ~SiStOrS. `,,]l )? +s-, q H 1 is level sensitive for output buffer control in modes 2 and 3. `Sk,.*'`:, !,:, ,$,fL~i~~gh Impedance* Level ,,~. ""+$~. ... :.. *J,',' .*:.\l.!~;.,~ ~, Level \"j:;~:Y ). ` ,V,:: Level "\>\ Le~#~ Risj~~~#& , $Le$l " .:$, .%} ,-,$:.$Y, .>)..,, ( ., :., DO-D7 RS ..~! ,,...'.>, `**:i.?'~. 11.?.%~j, "'~.pt>:, ,\\il, PAOPA7 PB@PB7 H1 2 H3 H4 ,f;$ ~~~:~$, ~'..$:a< , *V. ..':+, `" .>.-:,:t*:N!.+i]t,>. IIF ,+ ` ,3 S{J, .J.:&: .,<.+ =.l.. /,> ~W n ~cm2m " :. Figure 1-3. Logical Pin Assignment :'!: - .,,;+ .,{J.;:.>?!,\. ,,,.l+ .i,,$f~.*ReadlWrite (R/~) bus master, indicating whether read/write input signal from the MW~ `;~%~~ is a high-impedance bus cycle is a read (high) or write (low) cycle. " the current 1.2.4 Chip Select (=) ,,', C= is a high-impedance input that selects the Pi/T registers for the current bus cycle. Address strobe and the data strobe (upper or lower) of the bus master, along with the appropriate address ` bits, must be included in the chipselect equation. A low level corresponds to an asserted chip select. . 1.2,5 Data Transfer Acknowledge (DTACK) DTACK is an active low output that signals the completion of the bus cycle. During read or interrupt acknowledge cycles, DTACK is asserted after data has been provided on the data bus; during write cycles it is asserted after data has been accepted at the data bus. Data transfer acknowledge is CQ~. .,k<&..:.&:.$*,.. . patible with the MC68000 and with other M68000 bus masters such as the MC6B4W direct ~?$$~" access controller (DMAC). A pullup resistor is required to maintain DTACK high bet~%~f.8us ..::,*.t*\j . ..,." ,]>.:a~~ ,.,, 1.2.6 Reset (RESET} ~ k$;~ `r,,. ~T is a high-impedance input used to initialize all Pi/T functions. All con$~~$and data direction registers are cleared and most internal operations are disabled by the as,~~$~ of RESET (low), ,.??, ..t)..,8 .)s ~ "`i${k::*y' $... ,'\*\''.li,i, . .\h~\,:iy..?,. ,,.:$.. L 1.2.7 Clock (CLK) .,?:>,., .... ,,: `* \ ,,.. ,$,, ) --. The clock pin is a high-impedance TTL-compatible signal ,~i~$l$~b same specifications as the MC6BOO0.The Pi/T contains dynamic logic throughout, an~ ~~n~~his clock must not be gated off at any time. It is not necessary that this clock maintain a~~'particular phase relationship with the M6BOO0system clock. It maybe connected to an ind,~~endeht frequency source (faster or slower) ..:'~', .~f<{t, :.~t$t, as long as all bus specifications are met. ,:>~, :+}, ?? i,. .!!,? ,:3 \ ., ,, ~$,> s,.'..-,..,],:,*+ 1.2.8 Port A and Port B (PA&PA7 and PB@P&~~ .. Ports A and B are.& bit ports that may b,~~on'catenated to form a l&bit port in certain modes. The ports may be controlled in conjuncti~~~:wh the handshake pins H1-H4. For stabilization during system power up, ports A and B ~,~v&j~&rnal pullup resistors to VCC. All port pins are active high. .)..*>,, ... .,.0,!, ~t.w +;*, *J,. ` " ~.~?>:l'. )*m>\\ 1.2,9 Handshake Pins (H1-@$$~y' ..1:,,, ` `t]> - Handshake pins H1-H4 ,FG~~dfti-purpose pins that (depending on the operational mode) may pro vide an interlocked ,k~$hake, a pulsed handshake, an interrupt input (independent of data transfers), or simRld$~,Q pins. For stabilization during system power up, H2 and H4 have internal puilup resistors f~" `~~. The sense of H1-H4 (active high or low) may be programmed in the port general cont~aJCreg~ter bits 30. Independent of the mode, the instantaneous level of the handshake pins can b~~~w'from the port status register., *.., :<:JiFh.<:\y,: ,,.Jm,\/> ,,,\`.~?, , .,,:., $,fl<~klort can be used as eight general purpose 1/0 pins (PCGPC7) or any combination of six special , "">~mction pins and two general purpose 1/0 pins (PCOPCl). Each dual-function pin can be a stand"J3'~?l$~~rd or a special function independent of the other port C pins. When used as a port C pin, these 1/0 .,;~ },, ~ pins are active high. They maybe individually programmed as inputs or outputs by the port C data direction register. The dual-function pins are defined in the following paragraphs. The alternate functions TIN, TOUT, and TIACK are timer 1/0 pins, TIN maybe used triggered external clock input or an external run/halt control pin (the timer is in run/halt is high and in the halt state if run/halt is low). TOUT may provide an active rupt request output or a general-purpose squarewave output, initially high. ~ high-impedance input used for timer interrupt acknowledge. as a rising-edge the run state if low timer interis an active low ) -" 1-7 Port A and B functions have an independent pair of active low interrupt request (~1 rupt acknowledge (PIACK) pins. and inter- The DMAREQ (direct memory access request) pin provides an active low direct memory access controller request pulse for three clock cycles, completely compatible with the MCW50 DMAC. .:, t)!.," :::1,:..~ !,*:.-./.+ .?* x.,$ ,..,3..:bkt:,.,.. ~~ >, .>,$ `:!* , .,s>" 1.3 REGISTER MODEL `:.$.l.,., 33\~ ..-+>* 1.,,. .,>>3. .,,. *,?.>, A register model that includes the corresponding register selects is shown in Table 1-3., %;*!$" ,,.!JJ:!*$&' ,., ~,~,,,,,~?., *%. .'*?> c `,,+s ~. ,t\:.?.. {.\.t "~, "~?&$ ., \ Register Select Bits 543217 Table 1-3. Register,Model (Sheet 1 of 2) ., I 6 Port Mode Control 5 H34 Enable SVCRQ Select 4 H12 Enable 3 H4 Sense 2 H3 Sense 1 Port General Contol Register 00000 00001 00010 ..- * Bit 7 Bit 7 Bit 7 ,6' Bit 6 Bit 6 Bit IPF Select Bit 5 Bit 5 Bit 5' Bit 4 Bit 4 Bit 4.:$ Bit 3 Bil 3 ,$ Bit *v&% 3 ,oooli ,. :, 00100 P@rt ~~rrupt *tity ~o"trol .,. .~*!ikj "':~$ it B ` t\!\ ~ ,, ",:~ .> ,.'"! ` *+,,+" Bit 1 ~:$ .<$ Bit Bit' 2 1' * HZ Int Enable H4 Int Enable H1 SVCRQ Enable H3 SVCRQ Enable Bit 1 Bit , Bit 1 Bit 1 Bit 1 H2S q 00 Bit 0 Bit Port Service Request Register Port A Date . . ~%;ya~~ter Direction Register Port C Data Direction Register Pofl Interrupt Vector Register Port A Control Register Port B Control Register .,., Port A Data Register Port B Data Register Port A Alternate Register Port B Alternate Register Port CData Register Port Status Register (Null) (Null) , ( 00 00 0 Bit ,00 OF 0 q 00101 001'10 Port A Submode Interrupt Vec~$$J~i, `:' Numb,@ ,, `JS~-'*' ,$~+> ..: J 00111 .i:~.\~ q~ea,+'> #t,p,&~&5ntrol .$~ ~.s),:,;j!, ..$l~ ~,,,, .*\: .. *{.* `p.. `.y Port B $ .~t*k,& Submode $+ ~ .,>" H4 Control ~#,,:i.;,k*\.\. , ~*:F t:' Bit 7 Bit 4 ~ 6 Bit ,',., 6 Bit 6 Bit 6 H3 Level q HI 00 ` Stat Ctrl H3 Stat Ctrl Bit 00 01000 01001 :,., - Bit 3 Bit ~ Bit 3 Bit 3 Bit 3 H4S q Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 H3S q * q q 0 Bit 0 Bit q ~t ~~ ~t,'+ 5 Bit 5 Bit 5 Bit 5 HZ Level Bit 4 Bit 4 Bit 4 Bit 4 H1 Level q * .,, 0 1 0 1 Q* Ww 0 *J,, .,, :l,i > *A .*k"~~ 1 0 ~l;;t!$?:`*' Bit ~,,t>: ..;,, .,. y 7 gy , `?, Bit 7 H4 Level ** ** 0 Bit q 0 Bit q ., r:i .:.i, ~..,?:+w ,~ \*. .,,. .,. \ .k$]:?,~,* -.1,?, i$$:~,y$ 101 ,.., . ~i+r~? o *I "id :* o *** 0 HIS q qqqq $01110 * q * q 00 01111 q q q q q * 00 q q Unused, read as zero *Value before RESET * q Current value on Pins q q ..\ * q &Undetermined ValUe 10000 10001 10010 10011 h Bit 7 q TOUT/~ Contr( Bit 6 q Timer Interrupt Vwtor Register (Null) Counter Preload Register (High) Counter Preload Register (Mid) q 16 10100 1 , Bit 6 Bit 5 1 Bit 4 , Bit 3 *t@+74\ F"''"% ` .+.-, T' Bit 7 ` Bit 1 Bit 8 Bit 10101 0 Counter Preload Register (Low) (Null) lolll-m llOo Count Register (Hight Count Register (Mid) 1211 m ZDS q Or q * R:/Register Timer Status Register (Null) O0 < 00 00 1 q q q (Null) (Null) (Null) (Null) I I 00 00 00 < * NOTE Table 1-3 has been duplicated on foldout pages 1 and 2 at the end of this document for your convenience. I I \ 1.4 BUS INTERFACE OPERATION The Pi/T has an asynchronous bus interface, primarily designed for use with an M68000 microprocessor. With care, however, it can be connected to synchronous microprocessor buses. This section completely describes the P1/~s bus interface, and is intended for the asynchronous ~ ~*~.*. bus designer unless otherwise mentioned: ..V..,>., J,*, a),:!bsq:+~ .<+\v " `~".~ In an asynchronous system the Pi/T clock may operate at a significantly different frequency,, q~$~~'~ higher or lower, than the bus master and other system components, as long as all bus speci~@~Ws are met. The M C68280 CLK pin has the same specifications as the M C68000 CLK pin, a~~~d''not ..\\i.,> ,.\,\<.!, ,b,,t.:i%+y.k, .,,. ! .*9 be gated off at any time. ,, "$t~,, .x, .,. ~.~.,.:..a ,,*, ~! `iThe ftillowing signals generate normal read and `write cycles to the Pi/T: = {a Select), R/~ (read/write), RSI-RS5 (five register select bits); D&D7 (the 8-bit bidire~tiw'''~ata bus), and DTACK (data transfer acknowledge). To generate' interrupt acknowled~~~~~s, PC6/ PIACK or PC7/~ is used instead of ~S, and the register select pins are ignow~l~o combination of the following pin functions may be asserted simultaneously: ~, PIA~~~$~r m. ...:~:..\>\,, `*$., ;{, 4*$ ~\,.\A\ !*<, />' ...$.,$' .*. ~ .\-> ,,*;!, ,,*:> "\lFe\, 1.4.1 Read Cycles iig> ,<,.k,~. !.], This category includes all register reads, except port or t~~~~ri~brrupt acknowledge cycles. When ~S is asserted, the register select and R/~ inputs a~e.~t~ed internally. They must meet small setup and hold time requirements with respect to th~,,~~ed edge of ~S. (Refer to 6.6 AC ELECTRICAL SPECIFICATIONS for further informatid%$~$~he Pi/T is not protected against aborted (shortened) bus cycles generated.by an address er~prbr bus error exception in which it is addressed. ,$.$ ,, ,:,. \.$. ,, :.,.>;,\>, Certain operations triggered by normal re~. (~ write) bus cycles are not complete within the time ..w.h~ !,,.' ;, ( 1-1o ,, latched at the Pi/T's data bus interface at the same time =K is asserted. It is stable as long as chip select remains asserted independent of other external conditions. From the above discussion it is clear that if the chip select setup time prior to the falling edge of%~~}{ clock is met, the Pi/T can consistently respond to a new read or write bus cycle every foq~~J#W-' cycles. This fact is especially useful in designing the P1/~s clock in synchronous bus :~:%~~@not using DTACK. (An extra clock period is required in interrupt acknowledge cycles, seei!~~~~ inter.,! ,$,:, :{>.':..+ +i,~;k,t,p rupt Acknowledge Cycles.) .,, ~l. ,~i:<$~' >.,~,$.:.~icrt ~ ~y.~,$1+ In asynchronous bus systems in which the P1/7s clock differs from that$ofiw bus master, generally there is no way to guarantee that the chip select setup time with~~~mt to the Pi/T clock is met. Thus, the only way to determine that the Pi/T recognized the a~J@7& of = is to wait for the assertion of DTACK. In this situation, all latched bus inputs to the W{?tfibst be held stable until DTACK is asserted. These include register select, R/~, and write &f&~lnputs (see below). ,:$$.?:,.;J? . ., t,> ;%. -k:,&~:$.* System specifications impose a maximum delay from the ~~[~ (negated) edge of ~ to the negated edge of DTACK. As system speeds increase thi~~~~.~~es more difficult to meet with a simple pullup resistor tied to the DTACK line. ,Therefor@. t~t,P1/T provides an internal active puilup device to reduce the rise time, and a level-sensitive cit$~{t that later turns this device off. ~K is negated asynchronously as fast as p~ssible foll,o~~~ the rising edge of chip select, then three stated to avoid interference with the next bu+:3$&~ ~%.t.~;!, .i:,~ `. The system designer must take care that:D=K is negated and threestated quickly enough after each bus cycle to avoid interference wi~fi"~p next one_With an M~OOO this necessitates a relatively fast external path from, the data s~~@Jnegation to CS bus master ne9ation. ,,?}' `R* . \~~ ., .t;a}>,v. ,.., ?$*Y..,>:$~1.4.2 Interrupt Acknowled~~.~~~S Special internal operati?,~$~~~k"place on Pi/T interrupt acknowledge cycles. The port interrupt vector register or the tirn?~,v~tor register are implicitly addressed by the asseflion Of pC6/ plACK or ,' +>. ..+,.,,. $,'~~,,.x+').~ PC7/TIACK, respe@v~ly. The signals are first synchronized with the falling edge Of the clock. One clock period aft "}$@&$''are recognized, the data bus buffers are enabled and the vector is driven ,D onto the bu~,. ,+ $ K is asserted after another clock period to allow the vector some setup time prior to D~&,@~,~ DTACK is negated, then threestated, as with normal read or write cycles, when PIACK,,~~,m is negated. \ .~,,, ....,,.; `$*.\, ~;:h:*,, " Q*''~Grite ,.~,. Cycles \ <~ti%any ways, write cycles are similar to normal read cycles. On write cy~es, data at the DO-D7 pins :.,..,:,"% ~~ must meet the same setup specifications as the register select and R/W lines. Like these signals, ~,,. !/,.. wfite data is latched on the asserted edge of ~S, and must meet small setup and hold time re ";''" quirements with respect to that edge. The same bus cycle recovery conditions exist as for normal . read cycles. No other differences exist. i. 1-11 NOTE ` For mask sets GG7 and KD1 if the RS lines are selecting the port interrupt vector register (PIVR) or timer interrupt vector register (TIVR) during an interrupt acknowledge bus cycle then those registers may be changed. Four cases exist for this situation, they are: 1. Case: Results: 2. Case: Results: 3. Case: Results: 4. Case: Results: ~$,*, ......~*~.*. RS lines are addressing PIVR during a port interrupt acknowledge .,. f!'}~{,?.(,!~tt., . :*, ;$!P "~J ".*.>, * i `.. $ cycle (PIACK asserted). 4,*LL >... `J\?:,,<+, Incorrect IACK vector on data lines, bits O and 1 are zero, PIVR and ~~;;;~~s .,a~: .:, `.TIVR remain the same and are not changed. ,.,?, , .?,?,..> RS lines are addressing TIVR during a port interrupt acknowle@~~$Y ~ ,,,:; ~.},)l cycle (PIACK asserted). `, $1 incorrect IACK vector on data, lines, PIVR and TIVR areic~wed RS lines are ,addressing PIVR dpring a timer interrupt @"Wiedge ,.$,. "i'~>. !>...,SJ cycle (TIACK asserted). .~~. Incorrect IACK vector on data lines, PIVR and TIV:~$% changed. RS lines are addressing TIVR during a timer in~~~~t acknowledge . ... .s . *$,!~~ Correct IACK vector on data lines, PIVR ~~~!%i~*R remain the same and are not changed. ,4$. -,,.,,, ~,.:~+ ~, ,.,{l. ..-:.?, RS lines RS1-RS5 the above [" `\ For MC~OOO and MCWO1O systems that use AIF~$'for cases will never occur. A5 and A4 will remain ,,~" "$:. tiring interrupt acknowledge cycles ~v:.+$, v and thus PIVR and TIVR will not be selected ~&JShown below. ,., ., ~p#;\k, p RS4 ,, !'~~ RS3 RS2 RS1 MC03~ IACK Cycle `$$:$$?,. `:" 1 - Encoded Level - MC~230 PIVR Addres$~~$,~h o 1 0 1 MCW230 TIVR Add[~#~~~ 1 0 0 0 1 ,k +t~,~~ !,~t> ".. .. .,,,:..~ `l*' \,$**. ,,*.*i+.*?'.: -~.:<.e:tt fi,h $ \rl$.:;*41*,:"?:,:* ,~h.. .<,. ~+i, ~'k?., ,,}.t -`.~.+?. ,J$:j( t.J ..:*\. ` ~ .-*.** ij ,. .':>,:$' ~ ~ ,# ~:~. .+;~:g:,,p" ~'.~s ,,,, ,.`.~$. ~~*;k*&~ ~ti*?, :?.. ... .,..,~?.? ,m:, ,;~:\~,~ ,>+iy:.i,~ ,\\ ..'\>l>, !i. >.$" ``~ .-: \.r*,, \\\\.., \~\J{J+}7~t':\l,:t ~~.$.> ` , `*% ` ~.~:),,>t, .,\.ir ~t+::.t, SECTION 2 ,,X,. ""' `Q, PORT GENERAL INFORMATION AND CONVENTIONSPj~$'"+' `+if,$* .*..:,>. ?*?.. ,> *?<:,., ,,, , `t< "?/>,, ,iy This section introduces concepts that are generally applicable to the Pi/T po$}${,~d~~endent of the chosen mode and submode, For this reason, no particular port or handsm$$~~%s are mentioned; the notation H1(H3) indicates that, depending on the chosen mode a~,$~ ,,\T,.}:\*..\$ .:~i$. .,?j:> \ ,,., ,$.: . , . :a ,.~ .:f ,~;. . ~'. "Y+ ti.,? .i. .. ,~.:: ~'. -.;:;: ,~ $<.''$~$~. 2,1 UNIDIRECTIONAL VS BIDIRECTIONAL ,,*L ~i.~ $-$,t.:, ~\,,\y Figure 1-2 shows the configuration of ports A and B and *&ch bf the handshake pins in each port mode and submode. In modes Oand 1, a data directio~.@gis?&r is associated with each of the ports. These registers contain one bit for each port pin to ~a~,r%ine whether that pin is an input or an output. Modes O and 1 are, thus, called unidirectio@~~des because each Pin assumes a constant direction, changeable only by a reset conditi%~ak. a programming change. These modes allow doublebuffered data transfers in one directio~. . Mis direction, determined by the mode and sub,$8 mode definition, is known as the primar~~irectlon. Data transfers in the primary direction are controlled by the handshake pins. Data tr~.s%s not in the primary direction are generally unrelated, . and single or unbuffered data pat~s ~~~~~ \ .~<:+,,,a. *::* 9s?$. ~}. `.~>v% In modes 2 and 3 there is no,~ef of primary direction as in modes Oand 1. Except for port A in mode 2 (bit 1/O), the data ~lr%,%in registers have no effect. These modes are bidirectional, in that the direction of each tra@7e~%&fways8 or 16 bits, double buffered) is determined dynamically by the state of the handsha~@i~@#!Thus, for example, data may be transferred out of the Ports, followed very shortly by a ~~~~:@ into the same port pins. Transfers to and from the ports are independent and may occur f$~~y sequence. Since the instantaneous direction is always determined by the external sys~~~, a small amount of arbitration logic may be required. \,\k .. .l?+.. . . ~t,,+ . ..\,?.,,\J>:" ,1' 2.1.1 . *>t,.p.*.,, `t,t, ~~~{rd~ of Double Buffered Data Potis ` .,}?,,, .$(~,jf) G#We&ly speaking, the Pi/T is a doubl%buffereddevice. In the primary direction, double buffering ,,~?~w~ orderly transfers by using the handshake pins in any of several programmable protocols. "$~{~hen bit 1/0 is used, double buffering is not available and the handshake pins are used as outputs `:$j~br status/interrupt inputs.) .;?, Use of double buffering is most beneficial in situations where a peripheral device and the computer system are capable of transferring data at roughly the same speed. Double buffering allows the fetch operation of the data transmitter to be overlapped with the store operation of the data receiver. Thus, throughput measured in bytes or words-per-second may be greatly enhanced. If there is a large mismatch in transfer capability between the computer and the peripheral, little or no benefit is obtained. In these cases there is no penalty in using double buffering. --, 2-1 2.1.2 Double Buffered Input Transfers In all modes, the Pi/T supports doublebuffered input transfers. Data that meets the port setup and hold times is latched on the asserted edge of H1(H3). H 1(H3) is edge sensitive, and may assume any duty cycle as long as both high and low minimum times are observed. The Pi/T contains a port status register whose H 1S(H3S) status bit is set anytime any input data that has not been read by.. "?$. ..,,*?$ the bus master is present in the doubl%buffered latches. The action of H2(H4) is programmable~$?,:?x .,~':k, ." may indicate whether there is room for more data in the Pi/T latches or it may serve other purpqg+,> \.31w:~ ~ .,>.I-t!. .x,\: The following options are available, depending on the mode. * ,.;\,.,\$) ..: 1. H2(H4) may be an edgesensitive input that is independent of H1(H3) and the ~@s$&~ of port data. On the asserted edge of H2( H4), the H2S (H4S) status bit is set. It is @8S~$@by the direct method (refer to 2,3 DIRECT METHODLOF RESE~lNG STATUS), the-pin being ,. asserted, or when the H12 enable (H34 enable) bit of the port general con~:$lkister is zero. .:' 2. H2( H4) may be a general purpose output pin tfiat is always negated. T~&~~~${ H4S) status bit \ `*,\,. L,*,: is always zero. .,...< i;.3*s. $ 3. H2( H4) may be a general purpose output pin that is always assert~d.$$&H2S( H4S) status bit ,,\J.> l,li+~i is always zero. t,yw,%t,:.i.]:,.y).. 4. H2( H4) may be an output pin in the interlocked input hands~~$~~~otocol. It is asserted when the port input latches are ready to accept new data. It is nxg'wasynchronously following the asserted edge of the H1(H3) input. As soon as the inp~$latc%es become ready, H2( H4) is again asserted. When both double buffered latches are ~.-k.~>} H4) remains negated until data is fO~~{'+~2( ` ~' removed by a read of port A (port B) data regkte$ Thus, anytime the H2( H4) output is asserted, new input data may be entered by.@~*~g H 1(H3). At other times transitions of ,, H1(H3) are ignored. The, H2S(H4S) status bit ls''&~ays zero. When H12 enable (H34 enable) is ,,t*.' ,., zero, H2( H4) is held qegated. ~~ Y ,, .<: f; \.,,,,~ N,.~.i;$ ~ ,,, ,* k. ~.,t:$ ~5. H2( H4) may bean output pin in t~$~~sd input handshake protocol. It is asserted exactly as in the interlocked input protoc~@~@Q&neverremains asserted longer than four clock cycles. Typically, a four clock cycle.~@fs generated. But in the case that a subsequent H1(H3) asserted edge occurs bef~~~mination of the pulse, H2( H4) is negated asynchronously. Thus, anytime after theJ&&& edge of the H2( H4) pulse, new data maybe entered in the Pi/T doublebuftered inpu~[~$,~s. The H2S( H4S) status bit is always zero. When H12 enable (H34 enable) is zero, H2(@~4~~js held negated. ., . !<.! ,,t:,j X:"... ~!,* `-X$;* :;{. . A sample timing q~gr%m~~s shown in Figure 2-1. The H2(H4) interlocked and pulse input handshake protocols are s~~~~$?The ,DMAREQ pin is also shown assuming it is enabled. All handshake pin sense bits a~e~~uked to',be zero (refer to 4.1 PORT GENERAL CONTROL REGISTER (PGCR)); thus, the p}$$~re in the low state when asserted. Due to the great similarity between modes, this timing:&$~~aYfi is applicable to all doublebuffered input transfers. ,, `$~, la'. <<.,.,, ,," .$i\.,~<:, ,{l:*., .> ~ ~, ...!. s ~ ~,l~~PoubleBuffered Output Transfe~ ~Me'Pl/T supports double buffered output transfers in all modes. Data, written by the bus master to the Pi/T, is stored in the port's output latch. The peripheral accepts the data by asserting H1(H3), which causes the next data to be moved to the port's output latch as soon as it is available. The function of H2( H4) is programmable; itmay indicate whether new data has been moved to the output latch or it may serve other purposes. The H1S( H3S) status bit may be programmed for two interpretations. First, the status bit is a one when there is at least one latch in the doubl~buffered data path that can accept new data. After writing one byte/word of data to the ports, an interrupt , 2-2 . <. Data Register Read Port Data Data Register Read H1(H3) H2(H4) Interlocked `H2(H4) Pulse DMAREO , the data has been transferred to the peripheral. T@*A194H3S) status bit is set when both output latches are empty. The programmable op~ons of .ti$~Q#(H4) pin are given below, depending on the *+\\~l . `~i~,!~+c, >t,i .,,. ,>;X. mode. .. . HZ(H4) may be an edg+sensitive in~ut @n':!ndependent of H1(H3) and the transfer of port data. On the asserted edge of H2( Q4~k,the H2S( H4S) status bit is set. It is cleared by the direct method (refer to 2.3 DIRECT ~$~~@D OF RESE~lNG STATUS), the RESET pin being asserted, or when the HI 2 e~s~~%~m enable) bit of the port general control register is zero. H2(H4) may be a general-~$p$~~ output pin that is always negated. The H2S(H4S) status bit ,,., !;... ~.>"., !,,. `~:~~:,.: is always zero. .J:.i.,.,3:., ..... H2(H4) maybe a ge.o.~1-$urpose output pin that is always asserted. The H2S( H4S) status bit kt~ is always zero. ,,t~,~~)a~] { H2( H4) may be{n `@tput pin in the interlocked output handshake protocol. H2( H4) is asserted two clock ~~f~$~ter data is transferred to the doubl~buffered output latches. The data r~ mains stg~le''~~~ H2(H4) remains asserted until the next asserted edge of the HI (H3) input. At that ti&]~:,~2( H4) is asynchronously negated. As soon as the next data is available, it is tra~$~~Fh to the output latches and H2(H4) is asserted. When H2(H4) is negated, asserted tr%~~t~ons on H1(H3) have no effect on the data paths. As is explained later, however, in ~~~+~$~s 2 and 3 HI does control the thre~state output buffers of the bidirectional port(s). The .,,,,$3.$$2S(H4S) status bit is always zero. When H12 enable (H34 enable) is zero, H2( H4) is held .-.>.>.f~ ~{.:...! ~'s.?..:,k-~:,.,l ,\S., .~.:~,, negated. 4,$):$$1,:,, >.,,. , ~>.,$.4.5. H2(H4) maybe an output pin in the pulsed output handshake protocol, It is asserted exactly as \\~\. ~~.$ }: in the interlocked output protocol above, but never remains asserted longer than four clock cycles. Typically, a four clock pulse is generated. But in the case that a subsequent H1(H3) asserted edge occurs before termination of the pulse, H2( H4) is negated asynchronously, thus shortening the pulse. The H2S( H4S) status bit is always zero. When H12 enable (H34 enable) is zero, H2( H4) is held negated. --- A sample timing diagram is shown in Figure 2-2. The H2( H4) interlocked and pulsed output handshake protocols are shown. The DMAR EQ pin is also shown assuming it is enabled. All handshake pin sense bits are assumed to be zero; thus, the pins are in the low state when asserted. Due to the great similarity between modes, this timing diagram is applicable to all doubl%buffered output . transfers. " ..$,:. Data Register Write x \ / ~ .,. .<$$~~ ( t, Figure 2-2. DoublsBuffered Output Tra,~f .,.,,, .:,; ..,$, ,.p *, ~., C*.,,&*.*' ** ., ,,. *>,.., 2.2 REQUESTING BUS MASTER SERVICE ~.{t>q ...>..$. ~,., ..><, .x,$~~h. The Pi/T has several means of indicating a need f&Rservice by a bus master. F[rst, the processor ., may poll the port status ~egister. It contains &sta&s bit for each handshake pin, plus a level bit that always reflects the instantaneous state ot:%~~b$ andshake pin. A status bit is one when the Pi/T h needs servicing (i. e., generally when-,$H~~& master needs to read or write data to the ports) or "when a handshake pin used as a sirn#.@sj$tus input has been asserted. The interpretation of these bits is dependent on the chosen ,,~'F@$&nd submode. ~~..:,..,+,l $:,t, ?,,:, ~, , .>\&, . ,,.,.,,, . Second, the Pi/T may be @a~~#n the processor's interrupt structure. As mentioned previously, the Pi/T contains port ~.,,~~~,,$ control registers that configure the handshake pins. Other bits in these registers enable ~fi''?~terrupt associated with each handshake pin. This ,,interrupt is made ~, .+.\:,available through t~~~B~PIRQ pin, if the PIRQ function is selected. Three additional conditions are required for+~lR ~'~oi$beasserted:' 1) the handshake pin status bit is set, 2) the corresponding interrupt (servic#~~~:@st) enable bit is set, and 3) DMA requests are not associated with that data transfer (H~~~~# ~3 only). The conditions from each of the four handshake status bits and correspondin$$i@tus bits are ORed to determine ~. To clear the interrupt, the proper status bit must$~~~~red (see 2.3 DIRECT METHOD OF RESETTING STATUS). p;. "::!. .:..,:~>1~::> $,+.-.,../i\ ::~. t+ T~$tird method of requesting service is via the PC4/DMAREQ pin. This pin can be associated `~$~~'double-buffered transfers in each mode. If it is used as a DMA controller request, it can initiate kquests to keep the Pi/T's input/output doublebuffering empty/full as much as possible. It will not overrun the DMA controller. The pin is compatible with the MCWW direct memory access -; 2.2.1 Vectored, Prioritized Port Interrupts Use of MC68000-compatible vectored interrupts with the Pi/T requires the PIRQ and PIACK pins. When m is asserted while ~ is asserted, the Pi/T places an 8-bit vector on the data pins DO-D7. Under normal conditions, this vector corresponds to the highest priority enabled active p~J interrupt source with which the DMAREQ pin is not currently associated. The most-signifi~~f~~~' bits are provided by the port interrupt vector register (pIVR), with the lower ~0 bits su.~~l<~by prioritization logic according to conditions present when PIACK is asserted. It is impor~~~~~¬e that the only effect on the Pi/T caused by interrupt acknowledge cycles is that the y@~~&f,.& placed on the data bus. Specifically, no registers, data, status, or other internal states Qf*~~$F1/T are af~ .,,.` ~; ,+..,,,, fected by the cycle. < `.'s,..~i~i?.~ .. \,.Y ,. ~ .,> *,;;{, ~everal conditions may be present when the= input is asserted toJ~&~~~*. These conditions affect the Pi/T's response and the termination of the bus cycle. If the R~3+~@sno interrupt function selected, or is not asserting PIRQ, the Pi/T will make no response 4*= (DTACK will not be asserted). If the Pi/T is asserting PIRQ when PIACK is received, ~~~ Pl~Y will output the contents of the port interrupt vector register and the prioritization bits. if }@j~,~R has not been initialized, $OF will be read from this register. These conditions are sum~~~~e~ in Table 2-1. ,<\*\" .$., -:!+ .? `t$>. ,,!i$'~~,j*\ Table 2-1. Response to Poti.f~!@rupt by` ~Q\ Acknowledge I q ~.. *+ ,*V ..,,. >? m. I with Prioritization bits. , I 1 The vector table entrie~ti~t~e Pi/T appear as a contiguous block of four vector numbers whose .,,, common upper six q,~,;~~!brogrammed in the PIVR. The following table pairs each interrupt source with the 2-bit valu,e~~roi~idedby the prioritization logic when interrupt acknowledge is asserted (see 4.2. PORT SER~l~~ REQUEST REGISTER (PSRR)). ::':: ,.$~~' ~.~ ,,<:,J~' ..1,> ,:,,?, ~, ,<,, H3 source - `1O H1 source - 00 , \$l *',*$ *:& :.$$~ .i!?i!> \\, ~ ~ ~. H4 source - 11 -t:\, vr,~~ "H2 source - 01 -s;N+,\ \ll,.\ ,:,':, ' y ,,!;..,f'.:je .,,%;,!l .:}:,:.+ The uninitialized vector is ~:q~~g$'?eturned from an interrupt vactor register before it has been initialized. ..,$>~,$.< ->!~><{. ,>~~ `$<>? }\*!,:$.j :@; "".i>i,\'"" \ `\$] !, ~ ~x>~,,, `$ #~.~~Autovectored ,,.,.~}>,, , *..S ,.,',,,. ,,, Port lnterru~ts `~~Autovectored interrupts use only the pin. The operation of the PIIT with vectored and !~~;$autovectored interrupts is identical except that no vectors are supplied and the PC6/PIACK pin can ,x ~ be used as a port C pin. The direct memory access request (DMAREQ) pulse (when enabled) is associated with output or input transfers to keep the initial and final output latches full or initial and final input latches empty, respectively. Figures 2-3 and 2-4 show all the possible paths in generating DMA requests. See 4,2 PORT SERVICE REQUEST REGISTER (PSRR) for programming the operation of the DMA reques~., `gX.. $+*~t\. .,.$.1: \ ,,*,, ,, \..s ~ ,Tt.J\;::. bit. ~:~~{$.::,,, i$t} ~~i~..,~,: ~,t+~x, ,/::. DMAREQ is generated on the bus side of"the MC88230 by the synchronized* chip select. lf,~&$~ditions of Figures 2-3 or 2+ are met, an assertion of= will cause DMAR EQ to be as~kda+tiree Pi/T clocks (plus the delay time from the clock edge) after = is synchronized. _i4#mains asserted three clock cycles (plus the delay time f~om the clock edge) and is then,~e~~d. .+, , $ :~.!t.\:'Q; ..*,`J$,~, DMAREQ pulses are associated with peripheral transfers or are generated::@~~@''kynch ronized* H1(H3) input. If the conditions of Figures 2-3 or 24 are met, an assertion:~~~ H1(H3) input will cause DMAR EQ to be asserted 2.5 Pi/T clock cycles (plus the delay tim'$dm clock edge) after H1(H3) is synchronized. DMAREQ remains asserted three clock cycl~$~ly~the delay time from the ,,,!*,C . -'.:, !,. clock edge) and is then negated. `.k,~~,. \ ;,., ~,:, ,, ,ti,, :: .;J`$:~,.l ~, .' ,r {$:kt*?..`.,.,, Data in Output Latches ~;t s[-y . ~.,:,+. \`<>'i , No DMA Request `~%eral ,.z*: " Provides `tt Data in Input Latches (""--' [-y Bus Write DataI No DMA Request ..J!&*.,~\.,*\ ,\\ , ,",' ., `M)R>'&<~~'DMA> Bus Write 4 No DMA Request \@> ,., !.* ,*d.,\ ~*:it$t.J..tt." ~~,.., ... ~ `oDMARLB2Read \ a ~:k a Associated ~~$@tput,,Transfers "t>. \:$'>;*. \l:!, .$~:,..,, ~,,*,,,,~,tJ .$ ,. Figure 2-4. DMAREQ .Associated with Input Transfers In,,-'wmodes one or more handshake pins can be used as edgesensitive inputs for the sole pur,~$~~& setting bits in the port status register. These bits consist of simple flip-flops. They are set (to `%) by the occurrence of the asserted edge of the handshake pin input. Resetting a handshake status bit can be done by wfiting an 8-bit mask to the port status register. This is called the direct method of resetting, To reset a status bit that is resettable by the direct method, the mask must q Synchronized means that the appropriate input signal (H1, H3, or ~) has been sampled by tha Pi/T on the appropriate edge of the clock (rising edge for H1(,H3) and falling edge for ~). Refer to 1.4 BUS INTERFACE OPERATION for the exception concerning ~. If a bus access (assertion of fi} and a port access (assertion of H1(H3)) occur at the same time, ~ will be recognized without any delay. H1 (H3) will be recognized one clock cvcle later. \ `! contain a one in the bit position of the port status register corresponding to the desired status bit. For status bits that are not resettable by the direct method in the chosen mode, the data written to the port status register has no effect. For status bits that are resettable by the direct method in the ,]!. chosen mode, a zero in the mask has no effect. .. ...,,1. . ..::))-, `., *.,,A,::~l. .}>.:,~$ .tii~"..}.~ \< ",,:.+, /~ ,-`\/,. t.~,.,,!,.. *>:>,. 2.4 HANDSHAKE PIN SENSE CONTROL .3. :.b: ~. ,,.<.:~'. . ~5,5\Yl `++), The Pi/T contains exclusive OR gates to control the sense of each of the handshakemfl~~ether used as inputs or outputs. Four bits in the port general control register may be ~~~r$fimed to determine whether the pins are asserted in the low- or high-voltage state. As ~~tfi@tier control registers, these bits are reset to zero when the RESET pin is asserted, defaulli~ t~+asserted level ~;:'~i:;l .*,*.. lk,J., ~ to be low. ,..,$,~, r> ,,.,:ici, !'`".*~.~ *~*t: *. `~,i?:t,ijt " \\,;} :'\\ %$:,;\t l.!:{% ?,?!\:>..,&t<', .$>,. 2.5 ENABLING PORTS A AND B `~.k:,. `... ,$ .~}, Certain functions involved with doubl~buffered data transfers, t~~bdshake pins, and the status bits may be disabled by the external system or by the progr~@&? during initialization. The port general control register contains two bits, H12 enable an~~~>dnable, which control these functions. These bits are cleared to the zero state when the= pin is asserted, and the functions are ,s.~t .$.' `v~(% disabled. The functions `are the following: .:.!:, ,*::..:.',, `! p 1. Independent of other actions by the bus m~~%er,~$r eripheral (via the handshake pins), the P1/7s disabled handshake controller is hel~$$#e "empty" state; i.e., no data is present in the `~i.+ doubl%buffered data path. , 2. When any handshake pin is used tq,~et asimple status flip-flop, unrelated to doublebuffered transfers, these flip-flops are hel&{~S&$ to zero (see Table 1-1). 3. When H2(H4) is used in an,,~~%~}ed or pulsed handshake with H1(H3), H2(H4) is held negated, regardless of the 4~t@ mode,' submode, and p~maw direction. Thust for double buffered input transfers$:@~@rogrammer may signai a peripheral when the pi/T is ready to begin transfers by se~~$'~$%eassociated handshake enable bit to one. ~ >.,,*' (.*.$,,,,', ,., .~, ,, 2.6 PORT A AND q~~$#iNATE REGISTERS ,,,,..,.;>.+iv:. ` ~ ~-" `,.J In addition to thd~~$$t A and B data registers, the Pi/T contains port A and B alternate registers. These regist~~$are~ead only, and simply provide the instantaneous (non-latched) level of each port pin. They. ti$$~'~ effect on the operation of the handshake pins, doublebuffered transfers, status bits, or~~~her aspect of the P!/T, and they a}e mode/submode independent. Refer to 4.7 PORT 2-712-8 & $,*, f !'}~f,?.(,!kt?., :*, ~ ......~*~.*. SECTION 3 PORT MODES . `. i\: ,~$:.~ ll$:<. (,,, `?~it. "Kli,; .t.\\w `" t$,,.t:$!>!;& .>)> +`+ .!,<,.:$' ~ ,,,,. t,..' .,:?:,,..$ ,,:.,J' ..,..~,? `.$.$ ,yx:{'!i.3~ ~\ ,\lv? s$;%\ \*,*g" .\ ~ ,. .:~l:%.. % .ct~p This section contains information that distinguishes the various port modes aq~~~brnodes. General characteristics common to all modes are defined in SECTION 2 PORT ~~w~ INFORMATION AND CONVENTIONS. A description of the port A control register (@$$@} and port B control register (PBCR) is given before each mode description. After each s~~wde description, the pro~\ ~,,,, !* ,\ ,,<:Y.. \ .>. grammable options are listed for that submode. .:i:>3b,*::31:,t, .<,..>\,t `., \* ,\r,~J,*, . . }.s !!, !., .. .*(J,,,~ ,,.:.ss.\:,p,:.'" ",,' 3.1 PORT A CONTROL REGISTER ~$ijj ~:{ " Port A Control Regi~#~, (P~CR) ..,! ,,> 7 6 5 4 ,$y:t:$, `S* 2 1 H1 SVCRQ Enable 0 HI Status Control Port A Submode :+{\~.,,J&\p:*y:\\ Interrupt H2 Contro?;; ,., `" Enable \~ `..:$,~' H2 ., \'!\~t\ .s>t$..:~ The port A control register, in conjunc~d~,with the programmed mode and the port B submode, controls the operation of port A and t~$~~ntishake pins H1 and HZ. The port A control register contains five fields: bits 7 and 6 specif~~~~~rt A submode; bits 5,4, and 3 control the operation of the H2 handshake pin and the H2S -W<$$$bit; bit 2 determines whether an interrupt will be generated when the H2S status bit goes'watie; and bit 1 determines whether a service request (interrupt request or DMA request) wil&,~~~~" bit O controls the operation of the HIS status bit. The PACR is always readable and wfi~$h~y'" \2F** All bits are cleareQ~## when the RESET pin is asserted. When the port A submode field is rel~ vant in a mode/$&Q~$ode definition, it must not be altered unless the H12 enable bit in the port general con@~~fireglster is clear (see Table 1-3 located on foldout pages 1 and 2 at the end of this documenJ~:}~f&fing these bits will give unpredictable results. \ */ 7 Port B Submode H4 Control 6 5 4 3 2 H4 Interrupt Enable 1 H3 "SVCRQ Enable 0 H3 Status Control ,' .--' \ The port B control register specifies the operation of port B and the handshake pins H3 and H4. The port B control register contains five fields: bits 7 and 6 specify the port B submode; bits 5,4, and 3 control the operation of the H4 handshake pin and H4S status bit; bit 2 determines whether an interrupt will be generated when the H4S status bit goes to a one; bit 1 determines whether a service r~ quest (interrupt request or DMA request) will occur; and bit O controls the operation of the H3S status bit. The PBCR is always readable and writable. There is never a consequence to reading the register. 3-1 All bits are cleared to zero when the ~ pin is asserted. When the port B submode field is rel~ ` vant in a mode/submode definition, it must not be altered unless the H34 enable bit in the port "general control register is clear (see Table 1-3 located on foldout pages 1 and 2 at the end of this document). 3.3 MODE O - UNIDIRECTIONAL .\... .*<* . ,,,,$,+ .i .'%,,%.. > ,> ?,:, ,., ~ Submode 01 - Pin-Definable Double Buffered Output or Non-Latched Input $:$~~i~" Submode 1X - Bit 1/0 (Pin-Definable SingleBuffered Output or Non-La~$i~d `~'put) .. ..>, ,,~.,, ~i,<:! ~\~~. ?K:.%:JJ `Handshake pins HI and H2'are associated with pok A and configured by,,pg@$/*ming the PO~ A control register. (The H12 enable bit of the port general control register~~~q~es port A transfers. ) Handshake pins H3 and H4 are associated with port B and configurq b'?~rogramming the port B control register. (The H34 enable bit of the port general control ,!;J,*.:?\\ enables port B transfers. ) rek ::), The port A and B data direction registers operate in all three su~rn@&s. Along with the submode, they affect the data read and write at the associated data reg~t~~~cording to Table 3-1. They also enable the output buffer associated' with each port pin. ~:ke DMAREQ pin may be associated with ~~ither (not both) port A or port B, but does not functio~$~tfie bit 1/0 submode (submode 1X) is pro e +:,, $:] .':. . .. grammed for the chosen port. .! ,, ,,,$: ~'-~$.~, $,~ . ,$::?> `~$i 1'$,}1:: :,>.,}i~t,. +::>,, .. Table 31. ,~d~$ Po~ Data Paths ~,'~tkit\ ,,.. :,., ,., Mode Write Port Al B Data Rq'mer DDR=X FOL, S.B. ,, Abbreviat~ns: $ IOL ~':iti~$:6utput FOL Note 3 FOL Note 3 Latch 10L/FOL, D.B. FOL, S.B. Note 1 Note 2 Note 1 ., FQA *V ~jkl Output Latch ~r%~ ~nal Input Latch .,:.. ,,,~ Nx&~: \,&o\ *?.,. ~i``,*i:*: $!? , ,:, \,~..? `., ..r, ,. \.. ~.:> .+ e },:.* ~~ ~,pf:,, Note 2: ".&,& . +:.\)\>~ `" ..\>., ,*:&\'*> :;:,.$! Y+ Note 3: , .,t> ..*?"'::~+, .*J >` >$)". ;$; `}i*'*A*. "k./s :;.*. .+, . ttltt!>,$.~ ,.~... `~~~$.l S.B. - Single Buffered D.B. - Double Buffered DDR - Data Direction Register `"' Data is latched in the output data registers (final output latch) and will ~' single buffered at the pin if the DDR is 1. The output buffers will be turned off if the DDR is O. Data is latched in the double-buffered outpui data registers. The data in the finel output latch will appear on the port pin if the DDR is a 1. The output drivers that connect the final output latch to the pins are turned on. Subrnode 00 - Pin-Definable Doubl+Buffered Input or SingleBuffered Output `In mode O, doublebuffered input transfers of up to eight bits are available by programming sub mode 00 in the desired port's control register. Data that meets the port setup and hold times is latched on the asserted edge of H1(H3) and is placed in the initial or final input latch. H1(H3) is edge sensitive and may assume any duty cycle as long as both high and low minimum times are observed. The Pi/T contains a port status register whose H1S( H3S) status bit is set anytime any input data that has not been read by the bus master is present in the doublebuffered latches. The action of H2(H4) is programmable. The following options are available: 1. H2(H4) maybe an edg+sensitive status input that is independent of H1(H3) and the transfer of port data. On the asserted edge of H2( H4), the H2S(H4S) status bit is set. It is cleared by either the RESET pin being asserted, writing a one to the particular status bit in the port status register (PS R), or when the H12 enable (H34 enable) bit of the port general register is clea:f$$ 2. H2(H4) maybe a general-purpose output pin that is always negated, In this case the H2S$$M~$~ .,:. .'t , status bit is always clear. .~t:tt: `:.r,~:,,.o,>, 3, H2(H4) maybe a general-purpose output pin that is always asserted. In this case th~l~$\~4S) ,~~i~ . ,~:,..,,, status bit is always clear. $f+g ;..',~. 4. H2( H4) may bean output pin in the interlocked input handshake protocol. It-\{$'$##rted when the port input latches are ready to accept new data. It is negated asynchro~uwfollowing the asserted edge of the H1(H3) input. As soon as the input latches becom~@~dy, H2(H4) is again asserted, When the input doublebuffered latches are full, H2(H4) re~~j[~fiegated until data is removed. Thus, anytime the H2( H4) output is asserted, new iq~~~~:Kfa may be entered by asserting H1(H3). At other times, transitions on H1(H3) are iqnnor~: `The H2S( H4S) status bit is always clear. When H12 enable (H34 enable) in the por&&~@ral control register is clear, ,$*, Q "J , &,,..~,,, .,,.:, ,. ../ H2(H4) is held negated. 5. H2( H4) may bean output pin in the pulsed input handd~ks'$rotocol. It is asserted exactly as in the interlocked input protocol above, but nev~ refiins asserted' longer than four clock cycles. Typically, a four clock cycle pulse is gene~$~~! But in the case of a subsequent H1(H3) asserted edge occurring before termination :f$~h~$pulse, H2( H4) is negated asynchronously. Thus, anytime after the leading edge of t~@J}~&fi4) pulse, new data may be entered in the doublebuffered input latches. The H2S( H4S>wtatus bit is always clear. When H12 enable (H34 , For pins used as outputs, the data ~~%~%nsists of a single latch driving the output buffer. Data written to the port's data registert:i$~,,~'bt affect the operation of any handshake pin or status bit. Output pins may be used indep.~:w~ of the input transfers. However, read bus cycles to the data register do remove data frorn'~,&@}brt. Therefore, care should be taken to avoid processor instruc- 10 1 1 10 111 PACR 2 Output pin - as;erted, H2S is always clear. Output pin - interlocked input handshake protocol, H2S is always clear. Output pin - pulsed input handshake protocol, H2S is always clear. .-- .' ) ,, 0 1 H2 Interrupt Enable The H2 interrupt is disabled. The H2 interrupt is enabled. Programmable Options Mode O - Port A Submode and Port B Submode 00 (Sheet 2 of 2) 00 H1 SVCR Enable The H1 interrupt and DMA request are disabled. The HI interrupt and DMA request are enabled. PACR o x PBCR 76 00 PBCR 543 Oxx 100 101 110 111 PBCR 2 0 1 PBCR 1 0 1" PBCR o x 3.3.2 Submod~~O1. -*~in-Definable ,,<., ,,}) :: In mode O(,$~$$~W'~uffered output Double Buffered Output or Non-Latched Input transfers of up to eight bits are available by programming submode 01 @$b~~esired port's control register. The operation of H2 and H4 may be selected by program~rk@$%~ port A and B control registers, respectively. Data, written by the bus master to' the P1/T~[is ~?ored in the port's output latches. The peripheral accepts the data by asserting H1(H3), @&&$~auses the next data to be moved to the port's output latch as soon as it is available. G:*S .""~p :$, `,.~>:,!,k. "'~~he H1S(H3S) status bit may be programmed for two interpretations: . 1, The HI S( H3S) status bit is set when either the port initial or final output latch can accept new data. It is cleared when both latches are full and cannot accept new data. 2. The H 1S(H3S) status bit is set when both of the port output latches are empty. It is cleared when at least one latch is full. The programmable options of the H2(H4) pin are: 1, H2(H4) may be an edge-sensitive input pin independent of H1(H3) and the transfer of port data. On the asserted edge of H2( H4), the H2S( H4S) status bit is set. It is cleared by either the 3-4 k' * . RESET pin being asserted, writing a one to the particular status bit in the port status register (PS R), or when the H 1(H2) enable (H3(H4) enable) bit of the port general control register is clear. 2. H2(H4) maybe a general-purpose output pin that is always negated. The H2S(H4S) statuq@$~F ~c}~, ,:,,, is always clear. $:'~$+::f~~ .,+' 3. H2(H4) maybe a general-purpose output pin that is always asserted. The H2S[H4SJa~~~@g$bit $~$,-~"" is always clear. >?, *J` . ,.,,. L,,. 4. H2( H4) may be an output pin in the interlocked output handshake pro~q&.;#2(H4) is .,- :,J,, $*:$ asserted two clock cycles after data is transferred to the doublebuffered oN~~~~latches. The data remains stable at the port pins and H2(H4) remains asserted until ~Q$~ex?asserted edge of the H1(H3) input. At that time, H2( H4) is asynchronously negated:,,~~;~~en as the next data is available, it is transferred to the output latches. When H2( H4) iS!;w@'led, asserted transitions of H 1(H3) have no affect on data paths. The H2S(H4S) st~~j~t"is always clear. When .,$+ "+$. H12 enable (H34 enable) is clear, H2( H4) is held negated. 5, H2(H4) maybe an output pin in the pulsed output handsh~[$$~tocol. It is asserted exactly as in the interlocked protocol above, but never remains @#,~r~#dlonger than four clock cycles. Typically, a four clock pulse is generated. But in the@e'f~at a subsequent H 1(H3) asserted edge occurs before termination of the pulse, H2( ~~) is fl%gated asynchronously shortening the pulse. The H3S(H4S) status bit is always clear+W~&n H12 enable (H34 enable) is clear H2( H4) ~): , $& ,X is held negated. ,~, ,'.?}>i,r:? ~$~. .~t:,:,s.(~ ,:;.~.$. ~J~, For pins used as inputs, data written to the as~p~ated data register is doubl=buffered to the initial or final output latch, `but, t~~output buffer is disabled. ,&,.~\ `.. + at% ,,,, .", .:., h.i'..!,>~ ~>, ..,.~>,.:~t. .<:{: . Programm*~t$pfions Mode O - Poti A Submode 01 ,.~@/,@fi ,'. .\:*, "$ "~> :~>~,>,il ., ~f~f \ ., i,,w\,*' ~K Po_$,,@~.~#mode "i --- ; and passed B Submode 01 (Sheet 1 of 2) PACR 76 01 .... ,,i~ I~ PACR -.,f,. ,,\t ` f: * tii Control 543 .,,~?$)$::~ ` ..; O X X ,,(n~"N@n - edgesensitive status input, H2S is set on an asserted edge. pin --negated, H2S is always cldar. 1 0 ~l$&&*ut "1 ~~+ l%;~a:~~tputpin - asserted, H2S is always clear. .:$~~"'~l. "Output pin - interlocked input handshake protocol, H2S is always clear. ,3.;$*:'x." ,:y.1, 1~~ Output pin - pulsed input handshake protocol, H2S is always clear. r .*:L,,:.,,, ` .,..,"*$$~?PACR ry:. ., , ,yi.~ .t{,/:.,.* !${ 2 H2 Interrupt Enable .!, . 0 The H2 interrupt is disabled. 1 The H2 interrupt is enabled. PACR 1 Submodei~<.+,1$~ G~. `"$' >,<.,li::$ `" .'. .*?y+, . ~\:j\ ., o 1 -- 1 H1 SVCRQ Enable The H1 interrupt and DMA request are disabled. The H1 interrupt and DMA request are enabled. 3-5 Programmable Options Mode O - Poti A Submode 01 and Pofl B Submode 01 (Sheet 2 of 2) H1 Status Control The HIS status bit is set when either the port A initial or final output latch can accept new data. ltiw~~:i ,..\.'\.',: `,,~?:k,< is clear when both latches are full and cannot accept new data. The H 1S status bit is one when both of the port A output latches are empty. It is clear wh,~$g~~' 1 i ,:,$:1:\+\. least one latch is full. , \> !, ,,! ,:i~~,i `$.:(.2,' " *, .,,:> ,,.,:. , ~t~,La. -:s ,t:, \ ,x.. , ,.,:':', PBCR .s:..\:$:,,,%,>, . ~<$,,tk.' ~. ,tJ:\\~, Port B Submode 76 `~bt$:t~,, :;$ .....4).,,,?:,+ i ,, ,{ ~ !,, 01 Submode 01 PBCR 543 Oxx 100 101 110 111 PBCR 2 H4 Control lnDut Din - edgesensitive status input, H4S is set on an asserted WF ,.4,:L-4::$:,,,\ Output pin - negated, H4S is always cleared. ~:+i= .,y. .! ~...,$$. 4t*.*~>l$,i Output pin - asserted, H4S is always cleared. Output pin - interlocked input handshakeprotocol, H4S iq~~~$s cleared. afms~leared. Output pin - pulsed input handshake protocol, H4S is `:,~. >,> 0 1 ; PBCR 1 The H3 interrupt and DMA re~@$~redisabled. The H3 interrupt and DMA, ~~~es$ are enabled. ~,:+>< >s > ~.::>+,`.* . .'$,,\..+!,,,..,,. .V;4,. .4,..""~ PBCR + * $p/*~:t, ,0 H3 Status $o:~f.~ 0 The H3S status bi~ts *%&hen either the port B initial or final output latch can accept new data. It is clear when b~l~l~ai$hes are full and cannot accept new data. 1 The H3S stat~$ `a! `;s one when both of the port B outPut latches are emPtY. It is clear when at ,least one .J#%'*WJYull. "~~?~. ${$ s, \t,,: * (,* 0 ,'1' 3.3,3 Subrn&;f@ - Bit 1/0 (Pin-Definable SingleBuffered Output or Non-Latched Input} In mode,.~$~&k bit 1/0 is available by programming submode 1X in the desired port's control regist~txiw~submode is intended for applications in which several independent devices must be con~~dli@& monitored. Data written to the associated (input/output) register is single buffered. If or ~~~~~%~direction register bit for that pin is a one (output), the output buffer is enabled. If it is a zero ~~u~), data written is still latched, but is not available at the pin. Data read from the data register is ?:,, ~, ~ ,...\,: s;fti~ instantaneous value of the pin or what was written to the data register, depending on the contents of the data direction register, H1(H3) is an edgesensitive status input pin only and it controls no data related function. The H1S(H3S) status bit is set following the asserted edge of the input waveform. It is cleared by either the RESET pin being asserted, writing a one to the associated status bit in the port status register (PSR), or when the H12 enable (H34 enable) bit of the port as: general control register is clear. H2 may be programmed 1. H2(H4) maybe an edgesensitive status input that is independent of HI (H3) and the transfer of port data. On the asserted edge of H2(H4), the H2S(H4S) status bit is set. It is cleared by either the RESET pin being asserted, writing a one to the particular status bit in the port status i.. 3-6 Q register PSR), or when the H12 enable (H34 enable) bit of the port general control register is ` clear. 2. H2(H4)may beageneral-purpose status bit is always clear. output pinthat isalways negated. lnthiscase the H2S(H4S) >:>, H4 Interrupt Enable interrupt is disabled. interrupt is enabled. H3 SVCRQ Enable interrupt is disabled. interrupt is enabled. 3-7 Programmable Options Mode O - Pon A Submode and Poti B Submode 1X (Sheet 2 of 2) PBCR o x 3.4 MODE 1X H3 Status Control H3 is an edgesensitive status input, H3S is set by an asserted edge of H3. 1- UNIDIRECTIONAL 16 BIT MODE ~j?.s.::t. In mode 1, ports A and B are concatenated to form a single 16-bit port. The port B sub.~@~$~eld .*' . ..+>. .< `J"...?. ... .::$(:,. .... controls the configuration of both ports. The possible submodes are: "'"G;?, `" Pin-Definable Doubl&Buffer.ed Input or SingleBuffered &~~ut Port B Submode XO - Port B Submbde Xl - Pin-Definable Doubl&Buffered \ Output or Non-Latc~$$+~put ~1 ,\:$i ,$J,\,\ ~.`~..$ .-: \.r*,, :..$:,,*:,.>.:.,$ `!-:t:,':'.~$~' ~*.~\'i:\." tt$> J, .\,.r*, ~,.:.,;,.,. ~ .,,~$;;l .,, `,. `*~i/},3\l , .~,):~.' are associated Handshake pins H3 and H4, `configured by programming the POti B contrd;f~@ier, transfer. These 16-bit transfers are e%$~% by setting the HW \.s,':.>, , enable bit in the port general control register (PGCR). Handshake @@~HTand H2 may be used as simple status inputs not related to the l&bit data transferor H2 .~a~~e an output. Enabling of the HI and HZ handshake pins is done by setting the H12 enable bJt~~t,@ port general control register. The port A and B data direction registers operate in each sub'~~de. Along with the submode, they affect the data read and written at the data register a+.rdin~ to Table 3-2. The data direction register also enables the output buffer associated wi~e?~h port pin. The DMAREQ pin may be o,,~:tl*~,p `associated only with H3. ,$.. `.$ :>;:.. .~:$>s:*,~,r `1::... ~., , with the 16-bit double buffered ..-,, ( ...... . Mode Wine Port Al B Register Note 3 D. B., Note 1 D. B., Note 1 ,\&, ,,,1~ register is later written, }ort A data is'transferred to 10L/ FOL .Not&2: Data is latched in the output data registers (final output latch) and will be y!. single buffered at the pin if the DDR is 1. The output buffers will be turned ~s, off if the DDR. is0. Note 3: The output drivers that connect the final output latch to the pins are turned on. k ::: Abbreviations: IOL - Initial Output Latch FOL - Final Output Latch FIL - Final Input Latch S.B. - Single Buffered D.B. - Oouble Buffered DDR - Data Direction Register Mode 1 can provide convenient high-speed 16-bit transfers. The port A and port B data registers are addressed for compatibility with the M C6BOO0move peripheral (MOVEP) instruction and with the MC6B4W direct memory access controller (DMAC). To take advantage of this, port A should con-, tain the most-significant byte of data and always be read or written by the bus master first. The interlocked and pulsed handshake protocols, status bits, and DMAREQ are keyed to the access of port B data register in mode 1. Transfers proceed properly with interlocked or pulsed handshakes when the port B data register is accessed last. 3.4.1 Port A Control Register Port A Control Register (PACR) 7 6 Port A Submode H2 Contr61 5 4 3 2 H2 Interrupt Enable 1 H1 SVCRQ Enable 0 H1 Status Control .-:.:$,, \ ~.s:$.-,:: !;:?.::., .>\ ,4-J.\R., .-,> ,p'* ...i,~~:,. , ~a ~ *Y ,~+~,~ \ "$+,..:,i.r~ ,., .i -. ; The port A control register, in conjunction with the programmed mode and the port%,~$~~mode, controls the operation of port A and the handshake pins H1 and H2. The port A contr,@T,ge@lercontains five fields: bits 7 and 6 specify the port A submode; bits 5,4, and 3 control the~~wtion of the H2 handshake pin and, H2S status bit; bit 2 determines whether an interrupt wi~#&:~d$erated when the H2S status bit goes to one; bit 1 determines whether a service reque:~~$~$terrupt request or DMA request) will occur; and bit Ocontrols the operation of the H1S stat~ W&The PACR is always readable and writable. There is never a consequence to reading the r@&~~. :Ji:\~,$), .:,~y>,,, \.>..,\lt > `+::8 All bits are cleared to zero when the RESET pin is asserted. Wh~$tie ~. port A submode field is rele$:. \..1?: vant in a mode/submode definition, it must not be altered .m$ the H12 enable bit in the port general control register is clear (see Table 1-3 located on,Jpl"~,gt pages 1 and 2 at the end of this document). Altering these bits may give unpredictable,~e~~fis if the H12 enable bit in the PGCR is :::}.. ?~ set. .-! ~,+$> ,$.,,? ~.':~ :.:., ,. .!, .'>,>.?. ,J$b ,,). v... ,$ :,:)$c~p.. .w:.k.,.};;:>y*, 3.4.2 Port B Control Register ,. ,.,~'x .... . "*I> \ Poti B C:pntml Register (PBCR) ,7 pofl ~ Submode 6 ~ .$>,*;*:+? `" ,Jk' :ig:v< . ,i,J..i. * . ~:~+ Y* i+ ., ~ }i,l., ~$<.i~.\.$,\,F,t\><3. : H4 Control >'~$t,, ,~! ~ 3 2 H4 Interrupt Enable 1.0 H3 SVCRQ Enable H3 ` Status Control ~~?~4.3 .. .-- ,,j 1. H4 may be an edgesensitive status input that is independent of H3 and the transfer of port data. On the asserted edge of H4, the H4S status bit is set. It is cleared by either the RESET pin being asserted, writing a one to the particular. status bit in the port status register (ps R), or when the H34 enable bit of the port general control register is clear. 2. H4 maybe a general-purpose output pin that is always negated. In this case the H4S status bit .~+, "!,:,8., +,':s.;~y.. ,J:$i,:,t is always clear. ~.d,~f ,,,"...>> 3. H4 maybe a general-purpose output pin that is always asserted. In this case the H4S statu~~i~}-x' $*?, ,,et...,. ,./,>,,,? ,. is always clear. .~":' >, *$$:, 4. H4 maybe an output pin in the interlocked input handshake protocol. It is asserte$~~,~~b~'he port input latches are ready to accept new data. It is negated asynchronously,,/mW~g the asserted edge of the H3 input. As soon as the input latches become re~~i~$t~ is again asserted. When the ,input doubl~buffered latches are full, H4 remains ne~@ until data is removed. Thus, anytime the H4 output is asserted, new input data may,~~~tered by asserting H3. At other times transitions on H3 are jgnored. The H4S status M.~~~,@ays clear. When H34 enable in the port general control register is clear, H4 is held a~$d. 5. H4 maybe an output pin in the pulsed input handshake protoco~$~~j~.,asserted exactly as in the interlocked input protocol above, but never remains assert~Q~er than four clock cycles. Typically, a four clock cycle pulse is generated. But in th%q~x~~at a subsequent H3 asserted edge occurs before termination of the pulse; H4 is nrRg~%.@ asynchronously. Thus, anytime after the leading edge of the H4 pulse, new data ma~'s~, entered in the doublebuffered input latches. The H4S status bit is always clear. whe~''~~'knable is clear, H4 is held negated. ,+ 1-.! ,? , `!,, ::$), ?,,!: ,. - .. (, For pins used as outputs, the data path consists o~~tkngle latch driving the output buffer. Data written to the port's data register does not af$ect the operation of any handshake pin, status bit, or any other aspect of the Pi/T. Thus~' outpq~~~ may be used independently of the input transfer. 4$.?, , .$, 3. H2 may b,$$.g~n-erai-purpose output pin thatis always assefled. The H2S status bit is always i ., .. %. .+ \ Programmable Options Mode 1 - Port A Submode XX and Poti B Submode XO PACR 76 00 PACR 543 Oxx lXO 1X1 PACR 2 0 1 PACR ,1 0 1 PACR o `x PBCR '76 00 PBCR 543 Oxx 100 101 110 111 PBCR PBCR o x - H3 Status Control The H3S status bit is set anytime input data is present in the doubl+buffered input path. In mode 1 submode Xl, double-buffered output transfers of up to 16 bits may be obtained. Data is written by the bus master (processor or DMA controller) in two bytes. The first byte (most significant) is written to the port A data register. It is stored in a temporary latch until the next byte is written to the port B data register. Then all 16 bits are transferred to one of the output latches of ports A , and B. The DMAREQ pin may be used to signal a DMA controller to transfer another word to thet~$jk:,, port output latches. (The MC6B450 DMAC can be programmed to perform the exact transf~Y@J,+~ +t+~;k,tyr needed for compatibility with the Pi/ T.) H4 may be programmed as: ...,*,;.. . 1, H4 may be an edgesensitive status input that is independent of H3 and the transf~?~s~$~rt data. On the asserted edge of H4, the H4S status bit is set. It is cleared by either th~pin being asserted, writing a one to the particular status bit in the port status re*~~~~(~SR), or ,,::, ..::>,,,,. ,.,`.$i ` when the H34 enable bit of the port general control register is clear. 2. H4 may be a general-purpose output pin that is always negated. In this CF~~~~H4S status bit \. ,~i~>..' : . \ is always clear. > `?.?.,.$ $\,,:<: 3. H4 maybe a general-purpose output pin that is always asserted. In t$~:!~~e the H4S status bit ,.:. $'~::,i\:. is always clear. 4. H4 may be an output pin in the interlocked output handsp~$~$r~tocol. H4 is asserted two clock cycles after data is transferred to the doubl*buffer<@@,~~@ut latches. The data remains stable at the port pins and H4.remains asserted until the &$t asserted edge of the H3 input. At that time, H4 is asynchronously negated. As soon a$~e n&xt data is available, it is transferred to the output latches. When H4 is negated, asse~~@t~~*nsitions of H3 have no affect on data paths. The H4S status bit is always clear. Whe~& enable is clear, H4 is held negated. .i~~: .+ ~:+.~. 5 H4 may be an output pin in the pulsed outpuT*~;~Hdshake protocol. It is asserted exactly as in the interlocked protocol above, but n~~er.$$ernains asserted longer than four clock cycles. Typically, a four clock pulse is' genera$%,+But in the case that a subsequent H3 asserted edge `` occurs before termination of the,~~j~$h H4 is negated asynchronously shortening the pulse. The H4S status bit is always cl.@~@&]When HW enable is clear, H4 is held negated. ~.y\::l> ,,<.,> \+&,, .,. q:t ~.1,,, \* The H3S status bit may be pr~~@&ed for two interpretations: ~:1,,+ 1. The H3S status bit is ~~t %~$n either the port initial or final output latch can accePt'new data. It is clear when bo~Q~$t,$@es re full and cannot accept new data. a 2. The H3S status b~js~$et when both of `the port output latches are empty. It is clear when at least one latcw~s~fll~ .,''" .,,,$, `~,~:, .,.. ~$ .$:) ( The program~~~~,p'options of the H2 pin are: 1. H2 ~+~~~$an edge-sensitive input pin independent of H1 and the transfer of port data. On the a,,s~$f@edge of H2, the H2S status bit is set. It is cleared by either the RESET pin being ::@s#Med,writing a one to theparticular status bit in the port status register (PSR), or when the ,~$~,,~1$ enable bit of the port general control register is clear. ~%,.~$~"~2 may be a general-purpose output pin that is always negated. The H2S status bit is always ,,... ... . .?T,: `s " r clear. `} 3. H2 may be a general-purpose output pin that is always asserted. The H2S status bit is always clear. ( ..... 3-12 . For pins used as inputs, data written to either data register is double buffered and passed to the initial or final output latch, as usual, but the output buffer is disabled (refer to 3.3.2 Submode 01 Pin-Definable Doubl&Buffered Output or Nom Latched Input). . ,.< \, .t 543 ,\,qy ~: ~ ,,, R4 Control o x x ,,Jn~ui@ln1 0 ?,A'~~&ii*ut 1 Q:,~;*,L;@tput IJV+ ~. "Output Output ,@J,J:~:3:l,#~' .]}, ~~>:$,'#BCR lr+:~~..?"2 ~ edg~sensitive status input, H4S is set on an asserted edge. pin - negated, H4S is always cl~ared, pin - asserted, H4S is always cleared. pin - interlocked input handshake protocol. pin - pulsed input handshake protocol. o 1 H4 Interrupt Enable The H4 interrupt is disabled. The H4 interrupt is enabled. ---.' ) 313 Programmable Options Mode 1 - Port A Submode XX and Poti B Submode Xl (Sheet 2 of 2) PBCR 1 H3 SVCRQ Enable The H3 interrupt and DMA request are disabled. The H3 interrupt and DMA request are enabled. J*~~>, " ,`&., .,\t ,%=>,>):? ,\.>,.:.t: "!'~s,.>j, , *;?3,.,N..>::3, o 1 PBCR o 0 1 H3 Status Control . ,", ,)!:.:. , ;}~~ ~ .$'.i?*,t ~t ..~(~> .,.~.. ~ .. \ .i~~: ,~,$\. ,.!/., ,,.>$$ ` .'.:~$ 3.5 MODE 2 - BIDIRECTIONAL 8-BIT MODE `.$,+, ,, -.,!' In mode 2, port A is used for bit 1/0 with no associated handshake p~ns%~fi B is used for bidirectional 8-bit doublebuffered transfers. H1 and H2, enabled by the ~$~;~~able bit in the Port ge~eral control register, control output transfers, while H3 and H4, e~B$UY by the port general control register bit H34 enable, control input transfers. The instantan.~$pad~ection of the data is determined by the H1 handshake pin. The port B data direction re~s?&:Js not used. The port A and port B 2.:"+$., submode fields do not affect PI/T operation in mode .,,! ~:,,:, .,.,, ><:\, ., . ..><.. .J ! The H3S status bit is set when either the initial or final output latch of ports A an~~~,,;~m~ .}, accept new data. It is clear when both latches are full and cannot accept new d$?%?y~?~~ The H3S status bit is set when both the ini~al,and final output latches of Ports R w&,@are emPtY. The H3S status bit is clear when 61least one set of output latches is full. .:~,~ "+ -,... *3.*$. ?SJ> ..',.p~ * 3.. ~.~. ?;:8 ~ 3.5.1 Port A Bit 1/0 (Pin-DefinabIe .Singl+Buffer&@tput or Non-Latched Input) ..s. Mode 2, port A performs simple bit 1/0 with::go @%ociated handshake pins. This configuration is in:, tended for applications in whichseveral"'i n,@~ndent devices must be controlled or monitored. Data ~, ritten to the port A data register is si~~@~~ffered. If the port A data direction register bit for that w ,'; pin is set (output), the output buffeq$~:~~abled. If it is zero (input), data wtitten is still latched but not available at the pin. Data rea~i~~~~$fie data register is either the instantaneous value of the Pin (if data is stable from CS assert@~*Q@~ACK asserted, data on these Pins wilt be 9uaranteed valid in the data register) or what ~~~~r]tten to the data register, depending on the contents of the Port A data direction register. ,,~il:.\t.*.::. T.h&,i~Summarized in Table 3-3. `~ )..:!,:$ * t!:, :,i ..,' 3.5.2 port B - DoubleBuffered Bidirectional Data The output buffers of port B are controlled by the level of H1. When H1 is negated, the port B output buffers (all eight) are enabled and the pins drive the bidirectional bus. Generally, H1 is negated by the peripheral in response to an asserted H2, which indicates that new output data is present in the doublebuffered latches. Following acceptance of the data, the peripheral asserts H1, disabling the port B output buffers. Other than controlling the output buffers, H 1 is edg~sensitive as in other modes. 3-14 : ,< 3.5.2.1 DOUBLE-BUFFERED INPUT TRANSFERS. Port B input data that meets the port setup and hold times is latched on the asserted edge of H3 and placed in the initial input latch or the final input latch. H3 is edgesensitive, and may assume any duty-cycle as long as both high and low minimum times are observed. The Pi/T contains a port status register whose H3S status bit is set anytime any input data that has not been read by the bus master is present in the doubl~buffered latches T~E action of H4 is programmable and can be programmed as: ,t,!\'$qy1. H4 may bean output pin in the interlocked input handshake protocol. It is asserted ~~~~$~e port input latches are ready to accept new data. It is negated asynchronously f~~$~t~g the asserted edge of the H3 input. As soon as the input latches become read~~,~l~$s again asserted. When the input doubl%buffered latches are full, H4 remains negs$g~l,wtitii data is removed. Thus, anytime the H4 output is assefled, new input data may.~e "%,~$~~dby asserting H3. At other times transitions on H3 are ignored. The H4S status ~l$\@~lways clear. When H34 enable in the port general control register is clear, H4 is held ~&@$&H. .?:;:' ,. ,,S:*: 2. H4 maybe an output pin in the pulsed input handshake protocol. ~%J%Werted exactly as in the interlocked input protocol above, but never remains asserted ~~x than four clock cycles. Typically, a four clock cycle pulse is generated. But in the *that.*.* a subsequent H3 asserted ,it,,~. , edge occurs before termination of the pulse, H4 `is nept~'$$asynchronou sly. Thus, anytime after the leading edge of the H4 pulse, new data may:~~$ti$ered in the doubl~buffered inPut latches. The H4S status bit is always clear. When ~~ enable is clear, H4 is held negated. .,,{iw ~*Jk*>,, ~.s;i>,, 3.5.2,2 DOUBLE-BUFFERED OUTPUT TRANSF,@'#$Data, written by the bus master to the Pi/T, is stored in the port's output latch. The periphw~!~~~~epts the data by assefiin9 H1t which causes the next data to be moved to the port's output'"~xtih as soon as it is available. The H1S status bit, in the port status register, may be program~ed f~r two interpretations. Normally the status bit is a one when there is at least one latch in th@~@~Ol~buffered data path that can accePt new data. After writing one byte of data to'the portg?~,~~nterrupt service routine could check this bit to determine if it could store another byte; thg$~~~$fip's oth latches. When the bus master is finished, it is often b of the data has been transferred to the Peripheral. The H1S useful to be able to check wkiy~rdl !?, i:~~y,., `t:$,: status control bit of the ~ONt,,Aicontrol register provides this flexibility. The H1S status bit is set when both output latc~~}s~ empty. The programmable oPtions for H2 are: 1. H2 maybe an .~~~t$in in the interlocked output handshake Protocol. It is asserted when the port outpu$~~[%~ are ready to transfer new data. It is negated asynchronously following the asserted, eti~~~of the H1 input. As soon as the output latches become ready, H2 is again assertR~,When the output double-buffered latches are full t H2 remains asserted until data is re~,o$$}~~`Thus, anytime the H2 output is asserted, new output data may be transferred by $~~(?t%g H1. At other times transitions &n H1 are ignored. The H2S status bit is always clear. $sW~&n H12 enable in the port general control register is clear, H2 is held negated. f52.~~'2 may bean output pin "in the pulsed output handshake protocol. It is asse~ted exactly as in ,,.:*\,,:*\ ~ ,~.\ ,i,:..>,, .,~;:::,,,. ? ~.,,*,, .. ,$:> ~.'. ' the interlocked input protocol above, but never remains asserted longer than four clock cycles. " ~,,.. $%~' Typically, a four clock cycle pulse is generated. But in the case that a subsequent H1 asserted `?:'k-~.,, $,, :,~,. ~~ ~.),~p edge occurs before termination of the pulse, H2 is negated asynchronously. Thus, anytime \;+ after the leading edge of the H2 pulse, new data may be transferred to the doublebuffered output latches. The H2S status bit is always clear. When H12 enable is clear, H2 is held negated. The DMAREQ pin may be associated with either input transfers (H3) or output transfers (H 1), but not both. Refer to Table 3-4 for a summary of the port B data register responses in mode 2. 3-15 {-" Programmable Options Mode 2 - Port A Submode xx and Poti B Submode XX (Sheet 2 of 2) PBCR 1 H3 SVCRQ Enable The H3 interrupt and DMA request are disabled. The H3 interrupt and DMA request are enabled. o 1 `PBCR [?$,::.. ,,>, ,;.:s..~ ,.\*, ~` . ,? ,..-".'.~$ .! ., { k~'..>. "': ," \.:$,( 3.6 MODE 3 - BIDIRECTIONAL 16-BIT MODE .,:,... ?"~$">+:>, .. y> ` ~~j%:.i.:$. ~., ., .,*.! +.i.\?,. +$ . In mode 3, ports A and B are used for bidirectional 16-bit double buffer~~~;a%fers. H 1 and H2 control output transfers, while H3 and H4 control input transfers. H 1 a~~~~%~re enabled by the H 12 enable bit while H3 and H4 are enabled by the HM enable bit o{wt,h~;~'d~t9eneral control re9ister The instantaneous direction of data is determined by the H1 ha~~xke pin, thus, the data direction registers are not used and have no affect. The port A and pw'~~~$ubmode fields do not affect Pi/T operation in mode 3. Port A and port B butput buffers ar~$$~k$~lled by the level of H1. When H 1 is neaated, the output buffers (all 16) are enabied and t~% pins drive the bidirectional Pofl bus. Ge;erally a peripheral will negate H 1 in response to{~~~$erted H2, which indicates that new output data is present in the double-buffered latches. @ll'~~ng acceptance of the data, the peripheral asserts HI, disabling the output buffers. ot~j;$$~ controlling the outPut buffersl H1 is ed9esensitive as in other modes. The port A and,,+,.:, B data direction registers are not used. past ..,,$$ *>'J `: `"` i;~,.~ Port A and B input data that mex~,$eport setup and hold times is latched on the asserted edge of H3 and placed in the initial in~&$dt@h or the final input latch. H3 is edge-sensitive, and maY assume . ` `?2*&t `" any duty-cycle as long as b&~~$Tgh and IOW minimum times are obse~ed. The Pi/T contains a Port status register whose ~$$~~~tus bit is set anytime any input data is present in the doublebuffered latches that has not,~,:$,~@ad by the bus master. The action of H4,is programmable and can be Pro,)/ . grammed as: *:,, .,$ :$ 1. H4 may b~~~~~u'tput pin in the interlocked input handshake protocol. It is asserted when the port i~\t Iakhes are ready to accept new data. It is negated asynchronously following the asse~$&~.&#tige of the H3 input. AS soon as the input latches become ~ready, H4 iS a9ain aaw$$~ When the input double-bufferdd latches are fuIlt H4 remains ne9ated until data is .Q@~@oved.Thus, anytime the H4 output is asserted, new input data maybe entered by assert,$ ` r ;>'."';k~gH3. At other times transitions on H3 are' ignored. The H4S status bit is always clear. When ..x.*~,,+,~# enable in the port general control register is clear, H4 is held negated. H34 ,:Y: < `~, "l;$'<'s" ,i,(t.a:)i\~ 2. H4 maybe an output pin in the pulsed input handshake protocol. It is asserted exactly as in the ,,,\ :>,.r$,t.. `i >;i:{ interlocked input protocol above, but never remains asserted longer than four clock cycles. "$. Typically, a four clock cycle pulse is generated, But in the case that a subsequent H3 asserted edge occurs before termination of the pulse, H4 is negated asynchronously. Thus, anytime after the leading edge of the H4 pulse, new data may be entered in the doublebuffered input latches. The H4 s~atus bit is always clear. When H34 enable is clear, H4 is held negated. , 3-17 3.6.2 DoubleBuffered Output Transfers Data, written by the bus master to the Pi/T, is stored in the port's output latch. The peripheral accepts the data by asserting H1, which causes the next data to be moved to the port's output latch as soon as it is available. The H1S status bit, in the port status register, may be programmed for two interpretations. Normally the status bit is a one when there is at least one latch in the double*it, buffered data path that can accept new data. After writing one byte of data to the ports, an interj:,'~~~~~ box rupt service routine could check this bit to determine if it could store another byte; thus filling ~'w latches. When the bus master is finished: it is often useful to be able to check whether all of th~~~~$" has been transferred to the peripheral. The HI S status control bit of the port A control re~~$t&~~]Ovides this flexibility. The H1S status bit is set when both output latches are empty. T:$~~~~@ram\:i .2$4,,, ~ ,;, mable options for HZ are: `*<}$},?*. 1. H2 maybe an output pin in the interlocked ou~put handshake protocol. It is +$&ted when the ,~ $+. , i. r- . ( Mode 3 can provide convenient high-speed l~$it transfers. The port A and B data registers are addressed for compatibility with the MC68w~ahve peripheral (MOVEP) instruction and with the MCW50 DMAC. To take advantage ok~~~~~ofi A should contain the most significant data and alwa,ys be read or written by the bus ,Q~$~~first. The interlocked and pulsed handshake protocols, status bits, and DMAR EQ are keye~$$b access of port B data register in mode 3. If it is accessed last, the 16-bit doubl&buffered&+r%~~r proceeds smoothly. .,;{,, . ,.$*.,.+ i .,,.:?t,t, .:;~ The DMAR EQ pin may b~$-.~ted with either input transfers (H3) or output transfers (Hl ), but not both. Refer to Table ~-5$or a summary of the port A and B data paths in mode 3. ;,,{*i.~,~k:,$ ; ~ ~, ` ,l,.xtri:: Vj,,, :,? .` `I-t&>:t\*. .S,.*!,' ,. .+,.*. ~ ~:, $, )$p.$ I ,,.::.,. Table 3-5, Mode 3 Poti A and B Data Paths `J,s ~&" "$tir. ,,> ,*! ...x~i, ~. $, `$>$ >:$., , S)..$ -,,.~f:~ ,,,+.,,,,,,+ ".,1 ~ ,':1 )? \ !$... ..!,. s~.]...~$!< .!,K>.;? ~ *!*>.. .*,3! ~:~ ,f't;si> .i.,?i t$~J;;:::). `I;?:,$ -,), . Mode 3 Data Register FIL, D.B. Data Register 10L/FOL, D. B., Note 1 Note 1: Data written to Port A goes to a temporary latch. When the Port B data register is later written, Port A data is transferred to 10L/ FOL. Abbreviations: IOL - Initial Output Latch FOL - Final Output Latch FIL - Final Input Latch S.B. - Single Buffered D. B. - Double Buffered 3-18 SECTION 4 PROGRAMMER'S MODEL This section describes the internal accessible register organization as sqlster L RegiSer ,,~.??+ .,>,. (P&CR) I O I t )101010 . ` fj.. l*pSRR) I o I ( (.* ... ,], ~+?' .,. .,,<.,,, I po~ General Control Reqister I Poti Sewice Reauest Resister Port A Data Direction Resister ." !,>,.,.,. [ t 1 1 , , RW RW RW RW RW RW , I Yes Yes Yes Yes Yes No No No No No I I No Port B Data Direction Resister .= ..-- Port C Data Direction Register Port Interrupt Vector Register, Port A Cantrol Register Port B Control Register PortA Data Register Port B Data Register Port A Alternate Reoister .- .- ._=.-._. Pnfi___Altern ,late Register -. R . .. Port C Data Resister rur 1`-~ Status Register Tim Control Regis~#7 ler ler Tim Interrupt vectot~~ister Counter Prel@*$@~kter Counter Rq~@~ #gister I Count= .,,,,, ~~&~ Co:~qd@ter `kgister High Middle High Middle i ., (PBDDR)IOIOIOII (PCDDRt (PIVRI (PACRI 1 [ III 1 I lYesl [ Nol No No No No q I I ,.,. ,!?..., .:(, ~, ...`~' ,,~>, ,.F, -. ~i, K* , ". ,..,,,. ,: ... .. \ . ,,. , ,., f,.?, i ,?).,..:~ .,'.,, ..>, J>:. ,<{$*' \~ +?+.:,:l. \ ""w... *:.@> `~:! .:':,:>, .*.$.,,.>,> . ?.1 )Illolo o 0"' O111o1 "" 1 ,&J* `:*J ,,.:}: \./ ,,8 *,,,,~$,,,, ,.+jf ~ .. .? ".%t ,.. o o (PBCR) o (PADR) o (PBDR1 o (PAAR1 o (PBAR) 0 (PCDRI o (PSR) o (TCR) (TIVR) k (CPRM) (CPRL) (CNTRH) 011111 0 111 100 100 101 101 110 110 1000 1000 o 0 1 0 1 RW RW R R RW R * ** No No No o 11 .I ul 1 w, Yes Yes Yes Na No INOI I No No No Yes No No No No No 1 NO No No No No `w n RW RW RW R (CPRH)IIIOIOI1]l 1 Register Low 010o 10101 10111 1- u . n w f R R ` R I 1 ,,, k.., .,,.'_ . Lmt #oum{ Heglster Low , 1 (CNTRM) ,------[CNIHLJI1]l ITCS) ,, -,,,.." u " u " 0 1 o01 1 I ,-, `$$.f~"` " ~?;. q q q ".","" ,u~,-.v, \1I1 R w. A write to this register mav petiorm a special status resetting operatian. Mode dependent. R= Read W= Write Throughout this section the following conventions are maintained: 1. A read from a reserved location in the map results in a read from the "null register." .- The null register returns all zeros for data and results in a normal bus cycle. A write to one of these locations results in a normal bus cycle, but written data is ignored. and are read as zeros; written data is 2. Unused bits of a defined register are denoted by "*" ignored. ," 3. Bitsthat areunused inthechosen mode/submode butareused inothers aredenotedby ''X'', and are readable and writable, Their content, however, is ignored in the chosen mode/submode. ,:,Y .,, .Ffi .,,, , ,.,,;?, `,,;, !,, 4. All registers are addressable as 8-bit quantities. To facilitate operation with the MOVEP instruction and the DMAC, addresses are ordered such that certain sets of registers may also "':," \.:$,( be accessed as words (two bytes) or long words (four bytes)1 ?>..J.,\:<*;<>.,\:;:. :, ...$\,)+,. ..:..,,., ,,.$.h ~: J$ ,,,?,s,, ~ `t,. . * +!i.,,:,*,, 1.::,$ $T$\,\ $." ,.,,:,,. 4,1 PORT GENERAL CONTROL REGISTER (PGCR) 4.,' .~~> Poti General Control Register (PGCR) :",$~~~~ ,,.. 7 6 5 H34 Enable, 4 H12 Enable .3 2 H3 Sense 1 H2 Sense 0 Port Mode Control I H4 Sense The port general control register controls many ot the functions that a operation of the ports. The PGCR is composed of three major fields: bit tional mode of ports A and B and affect operation of the handshake pins allow a softwar~controlled disabling of particular hardware associ~$ each port; and bits 3-O define the sense of the handshake pins. ;!:/,,,~,s ,,y~, >= writable. ` :~i . ..A:+: L.*<$ :5,.. ,* . ,, All bits are reset to zero when the RESET pin is assert~$y,~w, .4:; ,,~~ ..>>.$~,, t, the H12 enable and H34 enable bits are The port mode control field should be altered on~~~~: zero.. Except when "mode zero is,desired (submod&{~F, the port general control register should be `` written once to' establish the mode with the, H1 #and H34 bits clear. Any other necessa~ control ~~ registers can then be program med;after ~mh H12 or H34 is set. In order to enable the respective operation(s), the port general control r~~$~r$hould be written again. ,,j, J,,jt ,, \..,. ,,. ~ ~$, ,\ PGCR 76 00 01 10 11 Mode Mode Mode Mode O (UnidirectiomJ &*#~ Mode) 1 (Unidirec@ha~l@- Bit Mode) 2 (Bidire:@#~[M-Bit Mode) 3 (Bidirq&ti@al 16-Bit Mode) .,,$.,,s,:;3{,, >.4:*1;.*F ...,$~ . ;., . Disabled Enabled 3-o 0. 1 Handshake Pin Sense The associated pin is at the high-voltage level when negated and at the low-voltage asserted. The associated pin is at the low-voltage level when negated and at the high-voltage asserted. level when level when ~ 42 e 4.2 PORT SERVICE REQUEST REGISTER (PSRR) Poti Service Request Register (PSRR) 7 q 6 SVCRQ Select 5 [ 4 3 Operation Select 2 1 0 Port Interrupt Priority Control "': ," \.:$,( ... a$$;;$;:i,~$.~,,s The port service request register controls other functions that are common to the overall op~r~t~h to the ports. It is composed of four major fields: bit 7 is unused and is always read as zerqkk~~~'~nd 5 define whether interrupt or DMA requests are generated from activity on the H1 $~~~$'handshake pins; bits 4 and 3 determine whether WO dual-function Pins oPerate as Po~..?:~t,@ofl interrupt request/acknowledge pins; and bits 2, 1, and O control the priority amon&~l[~~$8rt interrupt sources. Since bits 2, 1, and O affect interrupt operation, it is recommended,t~at . tWey be changed ::~:$i?:$$. only when the affected interrupt(s) is (are) disabled or known to remaj,~$t,~~~ve. The ps RR iS ,,~). i~.$:,:$ always readable and writable. $:. ,;, *.,/i.' :F$ `*t>,<>, !::,y,~. ~J$$.f$,:, ` ,$ib~ ,t,,.,t$;,l, All bits are reset to zero when the RESET pin is asserted. ~,,+ !;,, `:<~p~ *$:$S.:., .*,. PSRR 65 SVCRQ Select The PC4/DMAREQ *J.,s~\.,.,\, ,+,.i,.h*' .,,,,,;.: ,,!.. ,3,.>/. $"' ,., ;t~ `?~~, OX PSRR 10 "` 1 1 ` SVCRQ Select g $} The PC4/DMAREQ pin carries the -knction and is associated with doublsbuffered transfers controlled by H1. H1 is removs~~~% the pl/T's interruPt structure and thus? does not cause interrupt requests to be generatq~. ~G obtain DMAREQ pulses, port A control register bit 1 (Hl SVCRQ enable) must be a ~@{ The PC4/DMAREQ pin carrie~.ti$OMAREQ function and is associated with doubl%buffered transfers controlled by H3$,M'%~~$S&moved from the pl /T's interrupt structure and thus, does not cause interrupt requests$.~~~~,,s~nerated. TO obtain DMAR EQ pulses, POfl B control re9ister bit 1 pin carries the PC4 function$DWk is not used. .$P>:, $ .*,\ ...1..,,, ) v ~~,?,, `$' PSRR 43 carries the PC5 function, no interrupt support. nction, no interrupt support. 01 The P@/~Q pin carries the PIRQ function, supports autovectored interrupts. Th#$C6~FlACK pin carries the PC6 function, supports autovectored interrupts. in carries the pC5 funqtion. pin carries the PIACK function. in carries the ~ function, supports vectored interrupts. pin carries the PIACK function, supports vectored interrupts. port interrupt priority. .t)+~h ,, ~,,;!r . ,#'I$I&?, 1, and O determine The priority as shown in Table 42 is in descending left to right. Table 42. PSRR Port Interrupt Priority Control 210 000 Highest. . . . . . . . . . . . . . . . . ..Low@ HIS H2S HIS H2S H2S H1 S H2S HIS H3S H3S H4S H4S H4S H3S H3S 210 Highest . . . . . . . . . . . . . . . . . ..Low* H3S H3S H4S H4S H4S H4S H3S H3S HIS H2S HIS H2S HIS H2S HIS 100 101 001 010 011 110 111 I H4S I H2S 4.3 PORT DATA DIRECTION REGISTERS The following paragraphs describe the port data direction registers. 4.3.1 Poti A Data Direction Register (PADDR) ~ ~~~.~l The port A data direction register determines the direction and buffering characteristics of ea~,~~~ the port A pins. One bit in the PADDR is assigned to each pin. A zero indicates that the pin $(~~$$ as a input, while a one indicates it is used as an output. The PADDR is always rea@~@and writable. This register is ignored in mode 3. ,,$>.:,.,.:? .,,},. ,.~~ \ti) +- ,*<, ,,~?. ,.,,+-.., 4.3,2 Poti B Data Direction Register (PBDDR) "`i ,!i~,>it ! .;,\.:<, ~.\:\;\+ \,.,.,.* .::-$... ~ f,. .,,,,:.. , The PBDDR is identical to the PADDR for, the port B pins and the port .~~~~~''register, except that this register is ignored in modes 2 and 3. \ >. ..,+)$t ,Y,,, ~ -,,..,,, ~ r~:i,,t..?; ,Js ?;\{$,\ `~i,;. .;%b>z. ,,, `. ,. ( 4,4 PORT INTERRUPT "VECTOR ~&$~$?kR (PIVR) RQ~jf&f~rrupt Vector Register (PIVR) .. ~ 7 The port interrupt The contents of th iacknowledge b~p itors. Behavior.:*~~g a port interrupt acknowledge cycle is summarized in Table 2-1. ..\ .?J*.::$\, " I `rem a gd'm. ;ead ,cycle, there is never a consequence to reading this register. Following negation ()f thqJ,,RK~~ pin, but prior to writing to the PIVR, a $OFwill be read. After writing to the register, t:h:,,~~~~six bits maybe read and the lower two bits are forced to zero. No prioritization computal~,(bjperformed. `:?,:. `,?r.:ix., , .." ~\. ~ F5 PORT CONTROL REGISTERS (PACR, PBCR) 1`he port A and B control registers (PACR and PBCR) are described in SECTION 3 PORT MODES, 1`he description is organized such that for each mode/submode all programmable options of each. PIin and status bit are given. .,. The following paragraphs describe the port data registers. 4.6.1 Poti A Data Register (PADR) .-$ *-. ......,?,8,,,$ ~i,l{:st.,.},, \,>:t The port A data register is a holding register for moving data to and from the port A pins. Th@~~#A data direction register determines whether each pin is an input (zero) or an output (one), ,@*$j&&'ed in configuring the actual data paths. The data paths are described in SECTION 3 PQR%M~DES. .,- !\l, .~$," .~:w, ,~. ,,,:-,. .,,.Y.:,'-% ,:(:? This register is readable and writable at all times. Depending on the chose~j;~@W/submode, reading or writing may affect the doubl~buffered handshake mechanism. Th6\~o%~ data register ~A~.,:$* y$., .. . * !. is not affected by the assertion of the RESET pin. @\"+\',;, .$. ~][}i .?;:"' `~. ,..> .. \}$,*, $ *L> ~\~ ,.1,,~<$'$" `N.."'*!k .~ .>~:.?~!:?+:. 4.6.2 Pofl B Data Register (PBDR) $. The port B data register is a holding register for moving data t&~~&tfrom port B pins. The port B data direction register determines whether each pin is an inp~$~~~~b~or an output (one), and is used in configuring the actual data paths. The data paths are+~~~~ed in SECTION 3 PORT MODES. * `~\%. .', ~? This register is readable and wfitable at all time~,,~~@i4ending on the chosen mode/submodeI reading or writing may affect the doublebuffere,Q;$ari# shake mechanism. The port B data register is not affected by the assertion of the RESET*@M+;'""' .~.,.h, ., ... 4.6.3 Port C Data Regiqer (PCDR) ,,~~~% " The port C data register is a holdJp@~&i;er for moving data to and from each of the eight port C/alternatefunction pins. The$~~~~},~ardware accessed is determined by the tYPe Of bus cycle (read or write) and individual W@?&tins affecting each pin. These conditions are: 1) whether the pin is used for the port C or al~i%~ function, and 2) whether the port C data direction re9ister indicates the input or out~.. Table 43. PCDR Hardware Accesses ,+,,.. $... "i,. Note that two additional useful benefits result from this structure. First, it is possible to directly read the state of a dual-function pin while used for the non-port C function. Second, it is possible to generate program controlled transitions on alternatefunction pins by switching back to the port C function and writing to the PCDR. This register is readable and writable at all times and operation is independent of the chosen Pi/T mode. The port C data register is not affected by the assertion of the RESET pin. 4-5 4.7 PORT ALTERNATE REGISTERS The following paragraphs describe the port alternate registers. .*,,, . . .> .!:{' ..<*:, The port A alternate register is an alternate register for reading the port A pins. It is a rea@~~~~~ddress and no other Pi/T condition is affected. In all modes, the instantaneous pin level$~q# and no input latching is performed except at the data bus interface. Writes to this addre:q&+@{@swered with =, but the data is ignored. ,, ,7 ~ ,,,;(+~+ < ~w,.~. .,+$ .\.>,,. *+,. ...},~. ., ,. .\,, ,~,`., ~.,,,iit .*:~`(,:b. : \~ ,,:}.. 4.7.2 Port B Alternate Register (PBAR) , ,,, ~t, ~'i.;., `k):,.,s .' $*&. &,*,( ,!\ ,:,! It ,~.i The port B alternate register is an alternate register for reading the por&@*sJ .$h$ is a read-only address and no other Pi/T'condition is affected. In all modes, the instq~~~~us pin level is read and no input latching is performed except at the data bus interface. Wri@W'>'this address are answered with DTACK, but the data is ignored. ,.\*. ~${,fi ,\<\:, ,.31, ~i:i.:,{(. .? ,Wx.! ,,.>%. \..',:,\.\.\ ,. `,.:;!,, .,$,, pi f.? 4.8 PORT STATUS REGISTER (PSR) `~r\*,,i>fm ,,.$::-':,.,.3a ,,, > ~;,.,, ,!* Port Status Req@er `?@SR) 7 ,*,,?%*iq `k). 6 5 `4 H4 Level/ H3 Level I H2 Level I H 1 Le~lfj}, @S ~ ....::::* * 1 4,7.1 Port A Alternate Register (PAAR) 0 I HIS I I H3S I H2S s, The port status register contains information~~out handshake pin activity. Bits 7-4 show the instantaneous level of the respective hand$hakg pin, and are independent of the handshake pin sense bits in the port general control registq~~~: 3-O are the respective status bits referred to throughout this document. Their interpretationS*~nds on the programmed mode/submode of the Pi/T. For bits 3-O a one is the active or aq~~t?ti state. ,:>$:.. `*:i,%$.J$ ~w'>i;t,:.. ,-~, .,, .,,, ,,, 4.9 TIMER CONTROL R,~$~?+&~ (TCR) 9J;,$, 1+ `+:'i+b,<$ Timer Control Register {TCR) 5 4 Control 3 2 Clock Control 1 0 Timer Enable ~k',, &\)*\, ,.,~, The time~ carw the port C function. The dual-function pin PC3/TOUT carries the TOUT function. In the run state it is used as a square-wave output and is toggled on zero detect. The TOUT pin is high while in the halt state. The dual-function pin PC7/T~ carties the PC7 function. 4-6 .-> . 1 00 10 1 110 111 TCR 4 o 1 TCR 3 TCR 21 O0 The dual-function pin PC3/TOUT carries the TOUT function. In the run or halt state it is used as a timer interrupt request output. The timer interrupt is disabled; thus, the pin is always three stated. The dual-function pin PC7/_ carries the ~ function; however, since interrupt request is negated, the Pi/T produces no response (i. e:, no data or DTACK) to an asserted TIACK. Refer to .-:,.t.>, 5.1.3 Timer Interrupt Acknowledge Cycles for details. The dual-function pin PC3/TOUT carries the TOUT function and is used as a timer interrul~~@$l quest output. The timer interrupt is enabled; thus, the pin is low when the timer ZDS sta~ys,~~% one. The dual-function pin PC7/TIACK carries the TIACK function and is used as a time?~~~twpt acknowledge input. Refer to the 5.1.3 Timer Interrupt Acknowledge Cycles for detai~~~:~~fscom*::,Y ,:i*&:!>: bination supports vectored timer interrupts. J,.~,i~~ The dual-function pin PC3/TOUT carries the TOUT function. In the run or hal!st~~~,$~~sused as a timer interrupt request output. The timer interrupt is disabled; thus, the pin is "~~~ys thre%stated. ,%> ,,,.. ?.v$ ,,. The dual-function pin PC7/TIACK carries the PC7 function. %k,.{, . The dual-function pin PC3/TOUT carries the TOUT function and is ~.~#~~* timer interrupt re quest output. The timer interrupt is enabled; thus, the pin is IOWw%:w~~~~lmer ZDS status bit is one. The dual~function pin PC7/TIACK carries the PC7 functio~,,#~~Wtovectored interrupts are . .CY;;;. ?c,~$ `,, ~:, supported. *?, ~p?:s, *,1:, ,e ~ ,.x<:~,i,t `t>:b,~~ ~ ~.>.3\t, ,,..T?l,,) ~~; `-!$, Zero Detect Control ~ f$~t>..w>> The counter is loaded from the counter preload re~[~~r bri the first clock to the 24-bit counter after zero detect, then resumes counting. I:' .,,,.'.i+{ `* ,,i~ The counter rolls over on zero detect, then,~~~t%~es counting. .?$, n. ?1;,,,*,. .',..,, .~:$\,, !\.. ?>, ~~$,~$\t..:+::: :~::,,. Unused and is always read as zero. `Y$i, :$, ,.:~ *,<){;, ? \:;, t+}. ~$,.t. Clock Control The PC2/TIN input pin cawi~k~& port C function, and the CLK pin and prescaler are used. The prescaler is decremen,~,~:~p-"'the falling transition of the CLK pin; the 24-bit counter is decremented, rolls o,M&~~F~~&' loaded from the counter preload registers when the prescaler rolls over from $00 to $l$~q~ timer enable bit determines whether the timer is in the run or halt state. The PC2/TIN Qj@~~,@s as a timer input, and the CLK pin and prescaler are used. The prescaler is decremented 4P t@ %allingtransition of the CLK pin; the 24-bit counter is decremented~ rolls over~ or is load$~w~he counter preload registers when the prescaler rolls over from $00 to $1F. The timer i~,~~:~.~ftun state when the timer enable bit is one and the TIN pin is high; otherwise, the timer &kln$he haltstate: 01 T@,,PC~p~lN pin serves as a timer input and the prescaler is used. The prescaler is decremented ~~~g the rising transition of the TIN pin after being synchronized with the internal clock, The . +kk~:ti]t counter is decremented, rolls over, or is loaded from the counter preload registers when the ,.$t,:,.i ":$kpFescaler rolls over from $~ to $1F, The timer enable bit determines whether the timer is in the run .i*{tt.*. `$ "J'* `or haIt state. ~ -$<.,~~ ;, f~~,1$% The PC2/TIN pin serves as a timer input and the prescaler is not used. The 24-bit counter is ,$:, 1. ?$.:>:$ ,,,.,... decremented, rolls over, or is loaded from the counter preload registers following the rising edge ik~). ,,*JJ\~.*l. ..,. of the TIN pin after being synchronized with the internal clock. The timer enable bit determines .*:.,,. .:j'l::?)..: 4.10 TIMER INTERRUPT VECTOR REGISTER (TIVR) The timer interrupt vector register contains the 8-bit vector supplied when the timer interrupt acknowledge pin TIACK is asserted. The register is readable and writable at all times, and the same value is always obtained from a normal read cycle or a timer interrupt acknowledge bus cycle pin is asserted the value of $ (TIACK). When the ~ Timer Interrupt Acknowledge Cycles for more details. ,i..>s,''}i~ 4.11 COUNTER PRELOAD REGISTER H, M, L {CPRH-L) Counter Preload Register H, M, L (CPR 7 Bit 23 Bit 15 Bit 7 6 Bit 22 Bit 14 Bit 6 5 Bit 21 Bit 13 Bit 5 4 Bit 20 Bit 12 Bit 4 3'2 Bit 19 Bit 11 Bit 3 Bit 18 Bit 10 Bit 2 1 Bit 17 Bit 9 Bit 1 ~..,)$ The counter preload registers area group of three 8-bit registers u red to the counter. Each of the registers is individually addre with the MOVEP. L or the MOVEp.W instructions. The a! CPRH) is the null register and is resewed so that zeros ~r~ tion data register when a MOVEP. L is used. Data writ@ f&this address is ignored. ~:!, >,::,,, />1,< y$. These registers are readable and writable at all tj@~#~A read cycle proceeds independently of any transfer to the counter, which may be occurriq&~i,@ultaneously. To insure proper operation of the Pi/T timer, a value of $0~0 may not be s%~w `in the counter preload registers for use with the counter. The RESET pin does not affect th~ `&bntents of these registers. Register H, M, L (CNTRH-L) 7 Bit 23 Bi:20 Bit 12 Bit 4 3 Bit 19 Bit 11 Bit 3 2 Bit 18 Bit 10 Bit 2 1 Bit 17 Bit 9 Bit 1 0 Bit 16 Bit 8 Bit O CNTRH CNTRM CNTRL . .. -...\?.? ,,.,y The count register~'ar~;group of three 8-bit addresses at which the counter can be read. The con\,a ~'\:*, ,.,,,, ,{:+ tents of the ca&fitw"~re not latched during a read bus cycle; thus, the data read at these addresses ~":$.i ,t is not guara$tee&W the timer is in the run state. Write operations to these addresses result in a normal bus ~~~~~ut the data is ignored. `+,.,.\>,;.. ,+~>b,,. ~>,, . Each:$~~$eregisters is individually addressable, or the group maybe accessed with the MOVEP. L ~Vt~,MOVEP.W instructions. The address, one less than the address CNTRH, is the null register .$.q,djs reserved so that zeros are read in the upper eight bits of the destination data register when a f~#~OVEP. L is used. Data written to this address is ignored. .~, *<,i,, , `?%?$..,, /:. J$,>~&.:.+ ,\~~ 4.13 TIMER STATUS REGISTER (TSR) Timer Status Register (TSR) 7 q 6 5 4 3 2 I I q I 1 q I o 4 I q I q I q I ZDS 1 ~. , The timer status register contains one bit from which the zero detect status can be determined. The ZDS status bit (bit O) is an edgesensitive flip-flop that is set to one when the 24-bit counter decrements from $000001 to $000000. The ZDS status bit is cleared to zero following the direct reset operation or when the timer is halted. Note that when the _ pin is asserted the timer is ,,t.\.+,., di~ .. .,,: t~}is.it!i::: abled, and thus enters the halt state. ~$.?t~., `;! , . ,,..;, ,., ..:*J, ,.> ~.> :**,...$}, This register is always readable without consequence. A write access performs a direct r~d*3~&ra.*,,.,, ~' ..`r $. ,~.::::& ,:.~ ~~'~.. tion if bit O in the written data is one. Following that, the ZDS bit is zero. . ~~~ ,.$~ .,...>..>'~ ,. ..,.h,: 4-9/4-10 SECTION 5 TIMER OPERATION AND APPLICATIONS SUMMARy&~:$" ..,,, ,...,:!$ " $. ..:t.;( ~ ~?;., ,{;:(~.,, ` ->*k.. t::iy - This section describes the programmable options available, capabilities, and *&ictlons that aPPIY .?~`]$x. ).~.ytl~ to the timer. Programming of the timer control register is outlined with ,~~~~ gxamPles 9iven. ,.St}:.~,, .~.~, .,,t?~ \\.. 5.1 TIMER OPERATION The MC~230 timer can provide several facilities needed byy.~w oPeratin9 sYstems. It can generate periodic interrupts, a square wave, or a single inte$r~~t~~f~er a programmed time period. Also, it can be, used for elapsed time measurement or as *~#~v~ce watchdog. ~. ~..t: .-".~ , . .B ~:;ek,, ~- :.\J, The Pi/T timer contains a 24-bit synchronous downm~n~r that is loaded from three 8-bit counter preload registers. The 24 bit counter may be d,~~~~ by the output of a ~bit (divid~by-32) prescaier or by an external timer input (TIN). %~~w prescaler is used, it may be clocked by the system clock (CLK pin) or by the TIN external i~pu~. The counter signals the occurrence of an event primarily through zero detection. (A zerw~,when the counter of the 24-bit timer is equal to zero. ) This sets the zero detect status (ZDS) ,Q~%Jn*he timer status register. It may be checked by the processor or may be used to generate ~+~~~hterrupt. The ZDS bit can be reset by w~tin9 a one to the independent of timer operation. timer status register in that bit d@@ .~,>,.'~!:' ,\{\t*~?, ,,!>;:>;:.* ,*+?`,,,**, The general operation of thq.t~d? is flexible and easily programmable. The timer is fully configured and controlled by prog[~~~~~g the 8-bit timer control register (refer to 4.9 TIMER CONTROL REGISTER (TCR) for.,@d@Wnal information). It controls: 1) the choice between the port C operation and the timer~:@a&,~~onof three timer pins, 2) whether the counter is loaded from the counter preload register `~:,,rplls over when zero detect is reached, 3) the clock input, 4) whether the prescaler is ~,@#, and 5) whether the timer is enabled. T~~o~&~l $,$q'kdt state is determined by programming operation of the timer is described in terms of the run or halt states. The control of the the timer control register. When in the halt state, all of ,~.''}$~following occur ~~~~" 1. The prior content of the counter is not altered and is reliably readable via the count registers. ,3.. 2. The prescaler is forced to $1F whether or not it is used. 3. The ZDS status bit is forced to zero, regardless of the possible zero contents of the 24-bit counter. The run state is characterized by: 2. The counter is not reliably readable. 3. The prescaler is allowed to decrement if programmed for use. . 4. The ZDS status bit is set when the 24-bit counter transitions from $000001 to $000000. a 1. The counter is clocked by the source programmed in the timer control register. The following is a set of rules that allow easy application of the timer. 1 Refer to 5.1.1 Run/Halt Definition. 2. When the RESET pin is asserted, all bits of the timer control register are cleared, configuring the dual function pins as port C inputs. .-: .. . ::\lRk 3. The contents of the counter preload registers and counter are not affected by the W:pfh. The count registers provide a direct read data path from each portion of the 24-bit QQ'~~#r, but data written to their addresses is ignored. (This results in a normal bus cycle. ) ~~@~registers are readable at any time, but their contents are never latched. Unreliable .~~~g"'m~ybe read ~li ,,k,.'*. v when the timer is in the run state. .,.~,i`,:,~,.b,, .*?,.:.,. ,,x,..`J'it: The counter preload registers are readable and writable at any ~,~e ?~~,~this occurs independently of any timer operation. No protection mechanisms ar~+,$~~ided against ill-timed ..\~ .K>j :t+ writes. ,. .,.!?, The input frequency to the 24-bit cou;ter from the TIN ~ifi*&fi;:@rescaler output must be .:'~,.,: .. tk eight, between zero and the input frequency at the CLK pin divi,~ed~y :~$m, regardless of the con.,:{ ;:], , figuration chosen. ~.>~,> >..:$ ,\f,* . ~.`tl,,, 7. For configurations in which the prescaler is used (w~~~'~B CLK pin or TIN pin as an input), the contents of the counter preload register (CPR#~$ Wfisferred to the counter the first time that the prescaler passes from $M to $1F (roll,~;ov~~$after entering the run state. Thereafter, the counter decrements, rolls over, or is load~,{ `~k~mthe counter preload register each time the .. ,>. prescaler rolls over. +}. .. ., !~ 8. For configurations in which the presc@~&j~not used, the contents of the counter preload registers are transferred to the counter o)%he first asserted edge of the TI N input after entering the run state. On subsequent a:~rte&edges the counter decrements, rolls over, or is loaded from the counter preload regis$~r~i, , The smallest value allowed~t@&&ounter preload register for use with the counter is $-1. ,$y*$i. ~:i. "' ...*V,.: . ,$>~$. :F `~>,? ~ ,,~* ` 5.1.3 Timer' Interrupt Ack~"W~ge Cycles ..?:~?~, \ `}\+\& Several conditions m~ba~~tesent when the timer interrupt acknowledge pin (TIACK) is asserted. These conditions ~~$&&r,&e Pi/T's response and the termination of the bus cycle (see Table 51 ). $};'">*& 3$, ~,. ,t:>::::~,.$ `?).,. ,,>,., , .,. ~ ,, .,: ,i:il $.{ ., , ~*J.~,,\>, Table 51. Response to Timer Interrupt Acknowledge ,.) ,$:+~ >*$$` ,.~ik.i,,,l ` ,>,.,l~' *~ .J{.$r . .$+..),, ,+$+,,, PC3/TOUT Fun@ion ,,a:ti,-,,,:,,r<.\ ~ Response to Assaned TIACK \ .,i., J,*.* ..i$:,. ,. \ .~?y,~ "*:&,a,* $>, *$.?* `i)... ,, t. ,vi,$xi ..J:.},+y + ., ,,\.!!r ii:?.,:b~J~J, *i, ., ~+:<+ ,,.:.,\*.,.+ .,~,,V$ ., vu ~~, rPC3 - Port C Pin TOUT - Square Wave TOUT - Negated Timer Interrupt Request TOUT Asserted Timer Interrupt Request No Response No DTACK No Response No DTACK No Response No DTACK Timer Interrupt Vector content5 DTACK Asserted ~',~ ,' ,,,:,1 , ,,>.~.~ . ,~.- ..- 5.2 TIMER APPLICATIONS SUMMARY The following examples. paragraphs outline programming of the timer control register for several typical * \ 5.2.1 Periodic Interrupt Generator Example Petiodic Interrupt Generator Example 7 6 TOUT/~ Control 1 5 4 Z.D. Control 3 2 Clock Control Morl X 1 0 Timer Enable Changed .-:.r*,, \ ", ,',, ~. L-{'$:::.$\i+{,ii,.i ,$.!$>> "$.',. , `*,; ,.ki. ~,,' {.'!}. ,,, ~.?:$.~~?.$~:!+,),,',r q x 1 0 0 In this configuration the timer generates a periodic interrupt. The TOUT pin is conne~t&/& the system's interrupt request circuitry and the TIACK pin may be used as an interrupt ac~~~wpfige in,,,.i<\:\ },,.. t,.,. .,4.~t;y::~' ,,~*\' ~t. put to the timer. The TIN pin may be used as a clock input. t,,, `~,: , .?, $,, .~.$e,:<"~, . The processor loads the counter preload registers (CpR) and timer control r~~~@&(TCR) r and then enables the timer. When the 24-bit counter passes from $~Wl to $-,)'* ZDS status bit is set and the TOUT (interrupt request) pin is asserted. At the next cIocf:}~:&* 24-bit counter, it is again loaded with the contents of the CPRS and thereafter decrern,en~.;~h normal operation, the processor must direct clear the status bit to negate the interrupt~~l~est (see Figure 5-1). In this configuration the timer produces a square wave at the TOUT pin. The TOUT pin is connected to the usefs circuitry and the TIACK pin is not used. The TIN pin may be used as a clock input. The processor loads the counter preload registers and timer control register, and then enables the timer. When the 24-bit counter passes from $Hl to $m the ZDS status bit is set and the 5-3 TOUT (square wave output) pin is toggled. At the next clock to the 24-bit counter it is again loaded with the contents of the CPRS, and thereafter decrements. In this application there is no need for the processor to direct clear the ZDS status bit; however, it is possible for the processor to sync itself with the square wave by clearing the ZDS status bit, then polling it. The processor may also read the TOUT level at the port C address. ~*~.*. .....~~ .,., Note that the PC3/TOUT pin functions as PC3 following the negation of RESET. If used i~$?&j~*% square wave configuration, a pullup resistor may be required to keep a known level prior ~~$~$~ ,.\$$:)i'@ `J,:.s4,a gramming. Prior to enabling the timer, TOUT is high (see Figure S2). ,,,7,.<> .,,, ,.`!k:***~ "']:$ f, $~. /.)?. ~ .,,,~,,,j Enable ~ ! $FFFFFF 1 . . q Analog representation of ~h~\+&lUe. .. ...b,'!%:A [*...>.,,! ,. ~ *;,,: ..\ ;, ,. Figure 52. Square y~& .. ., :.. ,., ... ,. >? ~:~ Generator Example ,, 5.2.3 Interrupt After Timeout 7 \.$\ \ ,$:+:)s$,, ,$1\\,J,,. ..x `.':i,~~+ ,,::;+*, ~:t,. `s~ ih.,~b~rrupt Afier Timeout ~{;it\ Z. D. Control 1 1 q .*$ \,:y-,;, "T~: ~$, ,:, ~$' 1 Clock Control ~orlX 0 Timer Enable Changed TOU&{Tt . K ;**tofix ~{$s~,h.:x \* ,$t ,., 0 In this configuratio~+$~t~~er generates an interrupt after a programmed time"period has expired. The TOUT pin isco~@ted to the system's interrupt request circuitry and the TIACK pin maybe an interrupt ack~~~,dge input to the timer. The TIN pin may be used as a clock input. ,,.,,~, "$9**' . This conf~~~$on is similar to the periodic interrupt generator except that the zero detect control bit i:~8Xl!~s forces the counter to roll over after zero detect is reached, rather than reloading from .:,y~,t the ~~p~s. When the processor takes the interrupt it can halt the timer, read the counter and ~]~~[~~e the time from the interrupt request to entering the service routine. Accurate knowledge of -$$~~$interrupt latency may be useful in some applications (see Figure 5-3). .,.+>\,, '',:;:l `:,.:: ,,,,, . 5-4 -,<; 5.2.4 Elapsed ~me Measurement Examples Elapsed time measurement paragraphs. ,g+$x, `.J:.. > ~:. F:(*, .?i> "'++. , 5.2.4.1 SYSTEM CLOCK WMPLE. T~~~nfiguration allows time interval measurement by software. The TIN pin may be used as an..~brhal timer enable if desired. ,,+,.~~,.t forms are descfibed in the following takes several formq~.$+~~$ .&,:,.,:,. ;$J,R. `y.., \ ..,,,. \*, ., .tr~> f.! s The processor loa~~:~~~ounter preload registers (generally with all ones), loads the timer control register, and t@en`~~~les the timer. The counter is allowed to decrement until the ending event takes place. ~@~iit is desired to read the time interval, the processor must halt the timer and then read the wi~e}~ If TIN is used as an enable, thp start and stop counter functions are controlled . .>..,.,... FfQfi~,@iCations in which the interval may exceed the programmed time interval, zero detection can `$~:bunted by polling the status register or through interrupts to simulate additional timer bits. Note `~j}%*t the ZDS bit is latched and should be cleared after each detection of zero. At the end, the timer k. can be halted and read (see Figure 5-4). 5.2.4.2 UTERNAL CLOCK. This configuration allows measurementJ&$~fig) of the number of input pulses occurring in an interval in which the counter is enabled.,i~$$~l~lN input pin provides the input pulses. Generally the TOUT and TIACK pins are not used..i~fi$~" E~ernal Clock 7 6 TOUT/~ Control o 0 5 4 Z. D. Control 3 ,$! 8;$"* `& ~.::,, ,,. ,, ~ .,;* #,:'\;.>a ",',. ?+~:$~ ` 1 Clock Control .,$::$, ?$,~. .,.,..., ,:; $?..,~ } ... $ 0 ~mer Enable ~ ..~,~: ~ x changed This configuration is similar to the elapsed ti@~J&surement/system clock configuration except It can be connected to a simple oscillator that the TIN pin is used to provide the inpuf$@uency. and the same methods could be used. Alte.~ately, itcould be gated off and on externally and the number of cycles occurring while in t~q~run' state can be counted. However, minimum pulse width ,' x 1 Device Watchdog 4 Z. D. Control 1 ~ ..* .:1<,, ~tl~' ~,, ,-; 3 q Example 2 I 0 Clock Control 1 1 0 Timer Enable Changed 0 This c~~@%Stion provides the watchdog function needed in many systems. The TIN pin is the timeF:l~ptiVwhose period at the high (one) level is to be checked. Once allowed by the processor, ~~r.>., .:&,. th,~~!~,rnput pin controls the run/halt mode. The TOUT pin is connected to external circuitry re #uI{j~ notification when the TIN pin has been asserted longer than the programmed time. The ,f$+m pin (timer interrupt acknowledge) is only needed if the TOUT pin is connected to the inter,..> ,,,. ,:,,V,$J$, rupt circuitry. `~.;,' ~ ;+`t< ,3; ~!$. The processor loads the counter preload register and timer control register, and then enables the timer. When the TIN input is asserted (one, high) the timer transfers the contents of the counter preload register to the counter and begins counting. If the TIN input is negated before zero detect is reached, the TOUT output and the ZDS status bit remain negated. If zero detect is reached while the TIN input is still asserted, the ZDS status bit is set and the TOUT output is asserted. (The counter rolls over and keeps counting. ) 5-6 c, In either case, when the TIN input is negated the ZDS status bit is zero, the TOUT output is negated, the counting stops, `and the prescaler is forced to all ones (see Figure 55). , 57/58 This section contains electrical specifications and associated timing informatiQ~~t~r~e .t.if)i~, >*( i. 1:~} ~<> k,;\$, .. . li ~.~".,t$,l$ +:.,} ,,$,:*' , .,,$ s, ,, MC63230. `+"$~~ 6.1 MHIMUM Supply Voltage Input Voltage RATINGS Charatiefiatica symbol Vcc Vin Value -0.3 to +7.0 -0.3 to +7.0 o to 70 -Mto +Iao UnR ..1.", `iii?',$,*" ...... .>+ ~ .-. ..F Operating T@mn~r2t1Jre Ranae --------=. , TA I Tstg torage Temperature S1 This ~~~~ontains circuit~ to protect the iqw against damage due to high static v "~p or electric fields; however, it is adv ~F-'"~@ that normal precuations be taken to ,, Oc ,,,,:.~'i% application of any voltage higher than ,,i ,$+T$%$?oid maximum-rated voltages to this high`c ~'m~~.,~~$ "?:, impedance circuit. Ratability of operation is ,,,+,<::}+,, anhancad if unused inputs are tied to an ap~, ,\$,?...:st~?,?, \ :, propriate logic voltage level {e.g., either VSS The average chip-junctio~$@p#ratu re, TJ, in `C can be obtained from: (1) TJ = TA + (PD*6J#l~~J~JJ~ ,]$ Where: ,*:it<:*:(?*g,.dx ~ TA = A~b]$nt Temperature, `C 6J,#~~ Fa?kage Thermal Resistance, ,F&~@~NT+pl/O .,w:~~~T = ICC x VCC, Watts = Junction-to-Ambient, pOWer `C/W - Chip Internal ~,.w~,$~llo Power Dissipation PI/O Pins - User Determined Fo&1m6#%applications t?+.,,!;~ ,,\ ,,@l?)+: \:X.., ~&$&~PProXimate relationship between pD and TJ (if PI/O is neglected) :.\,>:.,., * .*,>f!$lP-PD= K- (TJ+2730C) `$*" ,,. `s Solving equations 1 and 2 for K gives: is: (2) K= PDO(TA+ 273C) +8JA*PD2 (3) Where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K the values of PD and TJ can be obtained by solving equations ( 1) and (2) iteratively for any value of TA. &l . . 6,4 DC ELECTRICAL CHARACTERISTICS unless othewise noted) Charamerimiu Input High Voltage Input Low Voltage Input Leakage Current (Vin = Oto 5.25 V) Hi-Z (Off State) Input Current (~"=0.4 (VCC = 5.0 Vdc + 5%, TA= O to 70C, Smw All Inputs All Inputs VIH VIL lin . 1.1 Mtn Vss + 2.0 Vss -0.3 k.. Vcc Vss+O.8 j,~,p~,, ,,,:, "''~?'" *:'- 4':* * . . ... v v ;; -A HI, H3, R/W, ~ES fi, CLK, RS1-RS5, ~~ to 2.4) bTAcK, pcGPc7. DO-D7 6.5 AC ELECTRICAL SPECIFICATIONS - CLOCK TIMING (see Figure 6-1) I I Chamaeristic ion w I I Smbl ! I I ~ I I f tm,,fi 8 MHz Min I Max Min 10 MHz Max 10.0 m 2W 2W In 12.5 MHz Min Max Unit MHZ 2,0 125 I I 8 ,0 ~ w m n 2.0 lm & * 4.0 80 % % -- 12.0 2M K II 6-3 6.6 AC ELECTRICAL SPECIFICATIONS (VCC=5.O Vdc *5%, unless othemise noted) 8 MHz Numbr 1 10) 2(1 11) 3[!, 4[2) 5 `6 7(3) 8 R/~, I= I -" ~ = Characteristic RS1-RS5 Valid to CS Low [Setup Time] Low to Rl~ and RS1-RS5 Invalid (Hold Time) I n,,, ," "L,. I n~v -",. *n ~1 K L"", (Setup Time) I .",, " VSS =0 Vdc, TA= OC to 70C, 10 MHz Mi~ ... I I Ma. .... .. 12.5 MHz Min ol- 60 20 I ) Min I , Max - w r- I I I I Max Unit ollml- 3o1I--17CI -- 1 I ol- 65 20 j / 1 - 0 itMl I I - 1, Low to P-+- n,,+ ~J-I:J "0,0 "UL Vallu .- I ,U mm RS1-RS5 Valid tn -.." n2f2n,I*vsliA ----". 1CVcle) o o 1 lM .- I I I o 0 1 c CLK LOW to DTACK Low (Read/Write = I 70 - 60 DTACK Low to ~ Hi$ (Hold Time) gh --_ or PIACK or TIACK High to Data Out Invalid .0 ! - .....t,..:. ..... , ,+..~,,:, 1" >>,. S,$:' ns I -- .,. ,9 (U-IA7;--! \l lulu t Illlel = ---- or PIACK or TIACK High to D&D7 High Impedance l"l-lol I .,-- } - 1 I - - 45 I ,,0 "i,J,:;-"-lq ,,,, I ..,, 45 I ns ns ns ns ns ns I 50 50 lm 10 11 12 13 14 lb 16 17 18 19 -", -, ~ or PIACK or TIACK High to DTACK High --_ --, = or PIACK or TIACK High to DTACK Hiah Imoedance -, Data In Valid to ~ = Low (Setup Time) Low to Data In Invalid (Hold Time) --_ ,:t~~" *7i$. ,+c~.>$@&:\" "' _ - "",.1. -. L ,,. , ,, , @::t>,&' %*,:** _ o f%~ `:' - - -1201 m 50 40 45 - - -ins 0 lW 100 20 - - Port Input Data Valid to HI (H3) Assertad (SetuD Time) I HIJH~l Assertad to Port Input Data Invalid UnlA Timn) , -f `*:W t:, $+~' ~ ,$~, 1201 ... . ,+IJY, 1 Handshake input HI (H4) Pulse Width Assertad Handshake Input H1 [H4t Pulse Width Negated H1(H3) Asserted to H2(H4) Negated (DelaV Time) CLK LOW to H2[H41 Asserted (Delav T , 4Q o`k#,* ,;'$*:<;&J _~.~:.$ ! . - 150 , I - I -- ,L, , ,7, naac, ,=" ~" m , ("Q, fi>~~, ~~" ..,:, `\:J}\. u u - 2.5 2.5 - 1.5 `- 0 0 I 40 lm 35 ns ns CLK Per. CLK Per, ns CLK Per. ns ns ns ns 21(5) 22(9,1 1) 23 24 25(9,1 1t 26 27 28 CLK Low to H2( H4) Pulse Negated (D,**] H1(H3) to CLK Low @+@f~% .,$$:+, > `$it:,}k~" DMAR EQ is Asserted ., ,.. CLK Low on which DMAREQ''~~ked'to CLK Low on which DMAREQh&~':~ted CLK Low to Port Out~?JD;@$alid (Modes O and 1).. \.*., ~ ,. Synchronized H1@3wrt (Modes O a*f&{$},;$ (DelaV Time) Synchronized "- .2.5 2.5 - 1.5 125 3.5 3 Im 2.5 70 o o 70 120 - 2.5 2.5 - 1.5 - 0 0 - I I 125 3.5 3 120 2.5 .50 70 100 3 100 2.5 50 70 - 60 Output Data Invalid H 1 Negated `?~:~'~ Output Data Valid (Mo@~ an&~) H1 A~8$$:@lo .Port Output Data High Impedance ,F$~Q&S q and 3) ~ ~~. Data Valid to DTACK Low (Setup Time) LOW to Data Output Valid, Interrupt 2~&~:* ;$t~ >., ,.. ,$ -. .-....-.-.--s..-. . . -7 -,- [ I `7' H1 (H3) .)$ I --,-...1- I `1 - -3 I I ns ns CLK Per. I i --_ r PIACK or TIACK LOW to CLK Low (Setup Time) Synchronized ~ to CLK Low on which k Asserted to Cl LK High (Setup Time) 5ol- w 3 3.5 o o 3 - 3 # 4ol- 40 3 I 3 I a 3 3.5 - 0 o 3 DMAREQ is Asserted XIY, I i) SVnchronizad H1(H3) to CLK LOW on which H2(H4) is Asserted CLK Low to DTACK Low Interrupt Acknowledge Cycle (Delay Time) CLK LOW to DMAREQj Low [Delay Time) CLK Low to DMAREQ High (DelaV Time) Synchronized H1(H3) to CLK Low on which PIRQ is Asserted 4,5 100 120 120 3 3.5 0 0 3 4.5 100 100 lm 3 -4.5 80 80 80 3 CLK Per. ns ns ns CLK Per. 34 35 36 37(111 64 -. ..< 6.6 AC ELECTRICAL Number 36(11} 3 SPECIFICATIONS Characteristic (Continued) 8 MHz Min 3 Max 3 250 3 10 MHz Min Max 3 225 12.5 MHz Min 3 Max 3 Unit Synchronized = to CLK Low on which ~ is High Impedance CLK Low to PIRQ Low or High Impedance TIN Frequency (External Clock) - Prescaler Used TIN Frequency (External Clock) - Prescaler Not Used TIN Pulse Width High or Low (External Clock) TIN Pulse Width Low (Run/Halt Control) 40(8) 41 42 43 44 45 o o o 55 1 1 1/8 - 250 - 0 0 o 45 1 1 118 - 0 0 0 45 "+~, JL .1., s . \,4~:T., ns CLK Per. _-- CLK Low to TOUT High, Low, or High Impedance -- ---- o % 0 L5 ., ~;i%' 2; ns CS, PIACK, or TIACK High to CS, PIACK, or _ TIACK LOW NOTES: .,t.~j~,., 1. This specification onlv applies if the PIIT had completed all operations initiated by t~,~~~jous bus cycle when~ was asserted. Following a normal read or write bus cycle, all operations are complete within t~p$~s after the falling edge of the CLK pin on which DTACK was asserted. If ~ is asserted prior to completion of these QQ~::LO~, the new bus cYcle, and hence, DTACK is ,.*. ` `~,..,.,: *+:~;t,:i? " postponed. .,`..+ .$; If all operations of the previous bus cycle were complete when=& asserted, this specification is made only to insure that DTACK is asserted with respect to the falling edge of the CLK pi~~~o% in the timing diagram, not to guarantee operation of the part. If the = setup time is violated, DTACK mav be as~~{,a~shown, or may be asserted one clock cycle later. .:... .,:.?\$~\ ,.!l:< .:r~, ~,, 2. Assuming the RS1-RS5 to data valid time has also expired~~~" ,.$~> Id..X1 ,$*\. ,.time, guaranteeing that ~ will be low for at least 1 CLK period. .,:~ ..-\c `~,,, .* ,,, 4. This specification assures recognition of thq *W edge of H1(H3). ,+\jt `~ ?<, "~:'>,,, ,1<* 5. This specification applies only when a a~,~~,~hdshake option is chosen and the Pulse is not sho~ened due to an earlv a=erted ..).,. s,,,~~ edge of H1(H3}. ~~ *,,+,. , ~ . f\. ~$..~l,t~ ..'.>...,i,l. ~!~$~ ,, *. 6. CLK refers to the actual freqV#kY ~+wp CLK pin, not the maximum allowable CLK frequencY@the ;,$:*,J 3. This specification imposes a lower bound on ~ ,., 7. If the setup time on th~~~~~,~ge ,?.~ ... ~:,,i, .1> of the clock is not met, H1(H3) may notbe recognized until the next fisin9 of the clock. 8. This limit applies ~@~~$~~~uency of the signal at TI N compared to the frequency of the CLK signal during each clock cycle. If any period of the wavdk~~at TIN is smaller than the period of the CLK signal at that instant, then it is likely that the timer circuit will completely j$~We ori~'cycle of the TIN signal. ,~$$$..> :.,,,. ,..,A; >.,:~i~ "'::,>,$\*p If the$~~,~~tghals are-derived from different sources thev Till have different instantaneous fraquencv variations. In this case the fr~~~~~~plied to the TI N pin must be distinctly less than the frequency at the CLK pin to avoid lost cycles of the TiN signal. ~+@~~bls derived from different crystal oscillators applied to the TIN and CLK pins with fast rise and fall times, the TIN fre ~":y~u~~v ~n approach 60 to 90% of the frequency of the CLK,signal without a loss of a cycle of the TIN signal. ~., ~.,j,., ,..$"i*. 1'* . . ... . ..~.. * , .? ~ .$.,,, jf these WO signals are derived from the same frequency source then the frequencv of the signal applied to TIN can be 100% of the :*,3,i, . ...*<< +s*.~.. `~,*.. frequency at the CLK pin. They may be generated bv different buffers from the same signal or one maybe an inverted version of .4.& ~..;$+:,:+., the other. The TIN signal may be generated bv an `AND' function of the clock and a control signal. ~... {.,. `\i), !. 9. The maximum value is caused bv a peripheral access {Hl (H3) asserted) and bus access (= 10. See 1.4 BUS INTERFACE OPERATION for exception. asserted) occurring at the same time. 11. Synchronized means that the input signal has been seen bv the Pi/Ton the appropriate edge of the clock (rising edge for H1(H3) and falling edge for =). [Refer to the 1.4 BUS INTERFACE OPERATION for the exception concerning ~.) Timing diagrams (Figures 6-2, 6-3, 6-4, 6-5, and 6-6) are located on foldout pages 3 4 5 and 6 at the ~ I. 7.2 ORDERING INFORMATION Package Type Ceramic L Suffix Frquency (MHz) 8.0 10,0 12.5 8.0 10.0 12.5 & Temperature O"c to 7o"c O"c to 7o"c .O"c to 7o"c O"c to 7o"c O"c to 7o"c O"c to 7o"c Order Number .-: \.r*,, ",>.'?., T4~: ,'r,,f?&:\t .,,,*\, ` ~ !<*.. ,S$ . "~* .!: . .,,!->., MCW230G8,a,i+~:$~A~:# M C08230~ $QjP Plastic G Suffix Lo .-- .-. .-. _ . .. --- ->-- , .,., DIM INCHES IWIILLIIJETERS MIN [ MAX I MIN I MAX , b L.D4 E J K I uI C--' 3.23 I./a Dab I V.UIU u ou I Table 1-3. Rwistw Mdei (Sheet 1 of 2) Mdel (Sheet 2 of 2) Vilua Ahw m 54321 00000/ 00001 {Ha 0000 10001 10010 10011 10100 10IO1 4i31210"b 00019 00011 00100 00101 iil.iil~)g 10110 .10111 11000 16 I 14 ait a . I I 1311 fit 6 . I I . . Oit I fit i s fir la sit 17 sit 16 w: 6 Wt .. .. COUnlM P(dmd lH@hl Pfdmd lMd) P,&d (Low) fl~ister Co"n!ef Rwkler Countw Rw61w Bit 90 MI ..* I I I 16 00 (Null) I 11001 11010 11011 ml 7 . I . q I ZD! 00 00 00 00 00 00 TImI fl~lsw( SHIUS (Null) (Null) INulll (NuIO {Null) 31100 .... . (Null) ...". 11101 11110 11111 Register Hgure 62. Raad CVcle ~~rrg Magram Foldout 3 Foldout 4 CLK - PA(PBI07 (MD 0.11 -, z ,f .,, ti PA(PBIOI (MD2,31 - a , figure&6. Peripheral Output ~ming Dagram .. . . . . .,.. ,.- -- q Motorola reserves !he right to make changes to any products herein 10 improve reliability, function or design. Motorola does not assume any IiabilitVarising out of the application or use of anv product or circuit described harein; neither does it convev any license under ifs patent rights nor the rights of others, . : .... .... ___ `,, . ._ (. ( `.-- (M) M~~oRo~A se~ic~nductor products Inc. 78721 q 3501 ED BLUESTEIN BLVD., AUSTIN, TEWS A SUBSIDIARY OF MOTOROU INC |
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